Intel Corporation

Roger I Kung

Jonathan Nick Spitz

Stephen T Flannagan

Joseph D Schutz

Perry H Pelley, Iii

Robert S Riley

Douglas J Covert

A CMOS dynamic RAM is described which uses multiplexing to selectively couple two pairs of bit lines to a single sense amplifier. Both pairs of bit lines are decoupled from the sense amplifier after a word line selects a cell and before sensing occurs in the sense amplifier. Only one pair of bit lines is coupled to the input/output lines of the memory. No dummy cells are employed. The bit lines are charged to one-half the power supply potential. Restoration of potentials on each pair of bit lines occurs at different times, thereby reducing the peak currents to the RAM.

CMOS dynamic random-access memory with active cycle one half power

A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.

Testing method and apparatus for dram

An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators if they are not operative after power is applied.

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Beaverton, OR, United States of America

Roger I Kung