Texas Instruments Corporation

Roger Griesmer

Bryan David Sheffield

Robert L Pitts

Vinod J Menezes

Joe W McPherson

Kevin L Kornher

John Ribe

David J Potts

Mark J Jensen

Kun-His Li

The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.

Contact fuse which does not touch a metal layer

An integrated circuit (IC). The integrated circuit comprises an array () of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry () for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry () for reading selected ones of the data cells in a read mode.

Integrated circuit with programmable fuse array

A method for testing an integrated circuit using a tester. The tester has internal periods for timing reference. The integrated circuit has one or more input ports, one or more output ports and a logic circuit disposed between the input ports and the output ports. The tester applies an input signal to one or more of the input ports, the input signal being synchronous to the internal periods of the tester, such that, by the operation of the logic circuit, an output signal appears at one or more of the output ports. The method comprises the following steps. First, a first output port is selected having a predetermined signal event that occurs at the first output port during a predetermined time range, the predetermined time range being determined with respect to the internal period. Then, the predetermined signal event is used as a timing reference for a test event of the integrated circuit, the test event occurring a predetermined time interval from the predetermined event.

Method for integrated circuit design and test

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Murphy, TX, United States of America

Roger Griesmer