Cypress Semiconductor Corporation

Asml Masktools Netherlands B.v.

Asml Masktools B.v.

Roger F Caldwell

Kurt E Wampler

Jang Fung Chen

Thomas Laidig

J Fung Chen

Tom Laidig

James Montague Cleeves

Jeffrey T Watt

Daniel J Arnzen

Ahmad Chatila

Kuantai Yeh

Johnathan G Bornstein

A method of forming a hybrid mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of forming at least one non-critical feature on the mask utilizing one of a low-transmission phase-shift mask (pattern) and a non-phase shifting mask (pattern), and forming at least one critical feature on the mask utilizing a high-transmission phase-shift mask (pattern).

Hybrid phase-shift mask

A method for making a mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of de-composing the existing mask patterns into arrays of &ldquo;imaging elements.&rdquo; The imaging elements are &pgr;-phase shifted and are separated by non-phase shifting and sub-resolution elements referred to as anti-scattering bars (ASBs). In essence, the ASBs are utilized to de-compose the larger-than-minimum-width mask features to form &ldquo;halftone-like&rdquo; imaging patterns. The placement of the ASBs and the width thereof are such that none of the &pgr;-phase shifting elements are individually resolvable, but together they form patterns substantially similar to the intended mask features.

Method of patterning sub-0.25&lgr; line features with high transmission, &ldquo;attenuated&rdquo; phase shift masks

Method of patterning sub-0.25 lambda line features with high transmission, &ldquo;attenuated&rdquo; phase shift masks

The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

Thin liner layer providing reduced via resistance

A method for forming a gap in a silicon layer is described. A silicon layer is formed over a substrate. A nitride layer is formed over the silicon layer and an oxide layer is formed over the silicon layer, adjacent to the nitride layer. A portion of the oxide layer is then removed to form an exposed region of the silicon layer. Then an etchant is applied to the exposed region to form an gap of the silicon layer.

Deep sub-micron polysilicon gap formation

A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.

Inverse open frame alignment mark and method of fabrication

The present invention provides a method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug of an associated contact or via hole. In accordance with the preferred embodiment of the present invention, a silicon substrate is provided having at least one device region formed at the surface of the substrate. An insulating layer is deposited over the substrate having at least one contact hole formed through the insulating layer to expose the device region. A first blanket layer of titanium is deposited as a tungsten adhesion layer over the insulating layer and the exposed device region within the contact hole. A second blanket layer of titanium-tungsten or titanium-nitride is then deposited as a tungsten barrier layer over the adhesion layer. Subsequently, a blanket contact plug layer comprising tungsten is deposited over the barrier layer by chemical vapor deposition. Both the contact plug layer and the barrier layer are then removed from the surface of the adhesion layer everywhere except within the contact hole by a selective etch back process wherein a selectivity between tungsten and titanium of at least 5:1 is achieved. Next, the exposed portions of the adhesion layer are patterned with a mask and etched to remove those portions of the adhesion layer not covered by the mask, thus converting the adhesion layer into a thin film interconnect or landing pad underlying the contact plug of the associated contact hole.

Method for the formation of interconnects and landing pads having a

A method for forming an alignment mark during semiconductor device manufacturing. A first alignment mark having a first step height is formed in a semiconductor substrate. An interlayer dielectric is formed over the alignment mark and planarized to a first thickness. During contact/via etch an opening is formed through the first dielectric layer away from the first alignment mark. The opening is then filled with a material until the material in the bottom of the opening has a thickness less than thickness of the planarized dielectric layer.

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Milpitas, CA, United States of America

Roger F Caldwell