Intel Corporation

Roger Espasa

Roger Gramunt

Guillem Sole

Julio Gago

Jesus Corbal

Edward Thomas Grochowski

Rolf Kassa

Santiago Galan

Toni Juan

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Mark Jay Charney

Joel S Emer

Federico Ardanaz

Jesus Corbal San Adrian

Geoff Lowney

Isaac Hernandez

Thomas D Fletcher

Andrew Thomas Forsyth

Manel Fernandez

Bret L Toll

Milind Baburao Girkar

Wei Wu

Ravi Rajwar

Eric A Sprangle

Sorin Iacobovici

Joshua B Fryman

Brian J Hickmann

Ramacharan Sundararaman

Jose Gonzalez

Ed Grochowski

John Cruz Mejia

Brian Hickman

Jairo Balart

David Guillen Fandos

Elmoustapha Ould-ahmed-vall

A processor includes packed data registers and a decode unit to decode an instruction. The instruction is to indicate a first source operand having at least one lane of bits, and a second source packed data operand having a number of sub-lane sized bit selection elements. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, stores a result operand in a destination storage location. The result operand includes, a different corresponding bit for each of the number of sub-lane sized bit selection elements. A value of each bit of the result operand corresponding to a sub-lane sized bit selection element is that of a bit of a corresponding lane of bits, of the at least one lane of bits of the first source operand, which is indicated by the corresponding sub-lane sized bit selection element.

Bit shuffle processors, methods, systems, and instructions

A processor for performing a vector permute comprises: a source vector register to store a plurality of source data elements; a destination vector register to store a plurality of destination data elements; a control vector register to store a plurality of control data elements, each control data element corresponding to one of the destination data elements and including an N bit value indicating whether a source data element is to be copied to the corresponding destination data element; vector permute logic to compare the N bit value of each control data element to an N bit portion of an immediate to determine whether to copy a source data element to the corresponding destination data element, wherein if the N bit values match, then the vector permute logic is to identify a source data element using an index value included in the control data element.

Method and apparatus for performing a vector permute with an index and an immediate

A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

Method, system, and apparatus for page sizing extension

Apparatus, method, and system for performing a vector bit gather are describe herein. One embodiment of a processor includes: a first vector register storing one or more source data elements, a second vector register storing one or more control elements, and a vector bit gather logic. Each of the control elements includes a plurality of bit fields, each of which is associated with a plurality of corresponding bit positions in a destination vector register and is to identify a bit from the one or more corresponding source data element to be copied to each of the plurality of corresponding bit positions. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a bit from the source data elements and responsively copy it to each of the plurality of corresponding bit positions in the destination vector register.

Method and apparatus for performing a vector bit gather

A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.

Method and apparatus for performing a vector bit shuffle

A processor includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating point data element. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, stores a result in a destination operand indicated by the instruction. The result includes a result floating point data element that includes a first floating point rounded sum. The first floating point rounded sum represents an additive combination of a second floating point rounded sum and the third floating point data element. The second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.

Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding

A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.

Super multiply add (super madd) instruction

Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.

Consecutive bit error detection and correction

Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction.

Indicating a length of an instruction of a variable length instruction set

A technique to generate a vector mask. In particular, at least one embodiment of the invention matches at least two instructions used in generating a vector mask and prevents at least one of the two instructions from executing if the correlation is found.

Technique for setting a vector mask

In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.

Implementing vector memory operations

In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.

Adaptively handling remote atomic execution based upon contention prediction

Growing community of inventors

Barcelona, Spain

Roger Espasa