Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Roger E Tipley

Alan L Goodrum

Barry S Basile

Mark E Taylor

Jeffrey C Stevens

Philip C Kelly

Mike T Jackson

Sompong Paul Olarig

Paul R Culley

Gary W Thome

Michael J Collins

E David Neufeld

Paul A Santeler

Michael P Moriarty

Maria L Melo

John A Landry

Jens K Ramsey

Jeff W Wolford

Robert Allen Pereira

Arthur G Volkmann

Walter G Fry

Thomas Turicchi

Steve L Radabaugh

Christina M Shaw

Systems and methods for managing information technology (IT) resources determine the physical location of at least one managed element using a property of the at least one managed element, wherein the managed element is assigned a unique name within a container and the property specifies a value that indicates the physical location of the managed element within the container, further wherein the value is provided in a format that is standardized for the type of container.

Systems and methods for addressing managed elements

Systems, methods, and other embodiments associated with automatically detecting and characterizing a power topology are described. One example system includes a topology logic that identifies connections between PDUs and computers that receive power from the PDUs. The example system may include a data store that receives PDU/computer association data from the topology logic. A computer may communicate with a power providing PDU over a power line connecting the two devices. The computer and the power providing PDU may be configured with network interface devices (e.g., Ethernet switches) configured to communicate over the power line using, for example, EoP. The topology logic may discover a PDU/CE association by examining data transmitted over a network to which the computer and/or the PDU are connected.

Automated power topology discovery by detecting communication over power line and associating PDU port identifier to computing device

The present invention provides for repeatedly pulsing coolant through a first channel exposed to heat-generating computer components. The pulsing involves a relatively low baseline coolant flow rate with repeated excursions to a relatively high expulsion coolant flow rate.

Coolant pulsing for computer system

Method, and apparatus for operating a power feed in a computing system. One exemplary embodiment includes monitoring the power feed to ensure the power level of the entire system never remains above a first power level and only remains above a second power level for a period of time determined by a timer level.

Method and apparatus for operating a power feed in a computer system

A server is capable of maintaining a power budget. The server comprises a central processing unit (CPU), a management processor, a power measurement circuit, and a comparison circuit. The comparison circuit receives real time power measurements from the power measurement circuit. A register includes a power budget value from the management processor. The management processor selects a system power performance state for the CPU that utilizes a level of power approximately equal to the power budget value.

Maintaining a power budget

A method determines actual power consumption for system power performance states (SPP-states) of a server. The method comprises initializing the server, performing a worst case workload test, measuring power consumption of the server at one or more SPP-states, and adjusting values in a lookup table to reflect the measured power consumption of the server.

Determining actual power consumption for system power performance states

A method of adjusting power budgets of multiple servers within a data center comprises various actions. Such actions include, for example, organizing the multiple servers into hierarchical groups, dividing a total power budget among the hierarchical groups, and assigning power consumption levels to individual members of a particular hierarchical group such that the sum total of the assigned power consumption levels does not exceed the total power budget for the particular hierarchical group. The act of dividing is dynamic with respect to time.

Adjusting power budgets of multiple servers

A system and method for connecting electrical components. More specifically, a method includes positioning a first set of electrical contacts of a first device opposite from a second set of electrical contacts of a second device, and activating a mechanism configured to rotate the first set of electrical contacts between an engaged position against the second set of electrical contacts and a disengaged position offset from the second set of electrical contacts.

System and method for connecting electronic components

A method for adjusting power consumption during server operation is disclosed. The method comprises initializing the server to a system power performance state (SPP-state) that comprises a plurality of constituent power settings, determining whether power regulation is required while the server is operating at the current SPP-state, setting a flag if power regulation is required, and increasing at least one of the plurality of constituent power settings associated with the SPP-state if the flag has been set.

Method and apparatus for adjusting power consumption during server initial system power performance state

Systems, methodologies, media, and other embodiments associated with selectively regulating power consumption by a computing system are described. One exemplary method embodiment includes receiving a signal that power regulation is desired for a computing system. The exemplary method embodiment may also include selectively causing a low power process to be executed in the computing system to cause the computing system to consume less power on average than would be consumed if the low power process was not executed.

Power management with low power processes

In general, in one aspect, the invention features a method for reducing the elapsed period between the time an interrupt acknowledge is issued by a CPU and the time when the corresponding interrupt vector is received at the CPU. When a device connected to a lower speed bus sends an interrupt request, an interrupt queue device, connected to the CPU by a higher speed bus, intercepts the interrupt request, temporarily stores the corresponding interrupt vector and then responds to an interrupt acknowledge from the CPU by delivering the temporarily stored interrupt vector on the higher speed bus. In addition, the interrupt queue can deliver the temporarily stored interrupt vector to the CPU on a separate serial line.

Reducing the elapsed time period between an interrupt acknowledge and an

Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Split transactions and pipelined arbitration of microprocessors in

Prioritization of microprocessors in multiprocessor computer systems

A computer system including the peripheral component interconnect (PCI) bus, including the LOCK# and STOP# signals and also having an extra sideband signal for supporting posted read transactions. The extra sideband signal, referred to as POST#, is used in conjunction with the LOCK# and STOP# signals defined in the PCI specification to implement the posted read. A posting target that determines that its read cycle is a long latency read, where the PCI bus should be released for non-exclusive accesses in the interim, asserts the STOP# and POST# signals to disconnect or retry the master and initiate a posted read. The master asserts the LOCK# signal in response to lock the posted target for the posted read, and then rearbitrates the PCI bus to other masters. Other masters may then access the PCI bus and perform non-exclusion access in the interim, while the posted target fetches the requested data. Masters requiring locked cycles or access to the posted target are disconnected or retried, or the cycle is otherwise aborted. Eventually, the original posting master regains control of the PCI bus, re-asserts the locked access and retrieves the data from the posted target.

Split transaction protocol for the peripheral component interconnect bus

A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Growing community of inventors

Houston, TX, United States of America

Roger E Tipley