IP Reservoir, LLC

Washington University

Exegy Incorporated

Becs Technology, Inc.

Sporlan Valve Company

IP Resevoir, LLC

Bfcs Technology, Inc.

Roger Dean Chamberlain

Mark Allen Franklin

David E Taylor

Ronald S Indeck

Scott Parsons

David Vincent Schuehler

Ron Kaplan Cytron

Jason R White

Joseph Marion Lancaster

Sharath R Cholleti

Kwame Gyang

Michael John Henrichs

Kevin Brian Sprague

Terry Tidwell

Praveen Krishnamurthy

Jeremy Daniel Buhler

Arpith Chacko Jacob

David C Macke, Sr

Chris Edmiston

Brett D Steinbrueck

Don Williams

Richard A Livingston

Joseph H Heffner

Viktor Gruev

G Thomas Seener

Benjamin Curry Brodie

John C Bell

Darko Ivanovich

Benjamin M Brink

E F Berkley Shands

Michael Henrichs

Jon G Metcalf

Joseph M Lancaster

Benjamin C Brodie

Ef Berkley Shands

Ronald K Cytron

Brett Steinbrueck

EF Berkley Shands

Systems and method are disclosed for distributed data processing across multiple compute resources. For example, the system may comprise a ticker plant configured to receive streaming financial market data events from a plurality of feeds, the events comprising financial market data pertaining to financial instruments. The ticker plant may comprise a processor, an FPGA, and a shared memory, wherein the shared memory is shared between the processor and the FPGA, wherein the processor is configured to execute software to manage a flow of financial market data derived from the streaming events between the processor and the FPGA via DMA transfers of the financial market data between the processor and the FPGA via the shared memory, and wherein the FPGA comprises reconfigurable hardware that is configured to perform processing operations on the financial market data to generate processed financial market data for delivery to data consumers.

System and method for distributed data processing across multiple compute resources

Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a structured format such as a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.

Method and apparatus for accelerated format translation of data in a delimited data format

Among the various aspects of the present disclosure is the provision of systems or methods for polarization division multiplexed (PDM) optical transmission. For example, the PDM optical transmission system can comprise a chip with one or more aluminum nanowire filters attached to the surface of the chip, such as division of focal Plane (DoFP) polarimeter filter array bonded on the receiver IC.

Polarization division multiplexed (PDM) communication systems and devices and methods of use thereof

A feature extractor for a convolutional neural network (CNN) is disclosed, wherein the feature extractor is deployed on a member of the group consisting of (1) a reconfigurable logic device, (2) a graphics processing unit (GPU), and (3) a chip multi-processor (CMP). A processing pipeline can be implemented on the member, where the processing pipeline implements a plurality convolution layers for the CNN, wherein each of a plurality of the convolutional layers comprises (1) a convolution stage that convolves first data with second data if activated and (2) a sub-sampling stage that performs a member of the group consisting of (i) a max pooling operation, (ii) an averaging operation, and (iii) a sampling operation on data received thereby if activated. The processing pipeline can be controllable with respect to which of the convolution stages are activated/deactivated and which of the sub-sampling stages are activated/deactivated when processing streaming data through the processing pipeline. The deactivated convolution and sub-sampling stages can remain instantiated within the processing pipeline but act as pass-throughs when deactivated. The processing pipeline performs feature vector extraction on the streaming data using the activated convolution stages and the activated sub-sampling stages.

Method and apparatus for hardware-accelerated machine learning

A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and hardware description code, wherein the hardware description code is compilable into a plurality of bit configuration files for loading onto the FPGA, wherein each bit configuration file defines a pipelined processing operation for a hardware template. The FPGA comprises configurable hardware logic, and the FPGA can be accessible over a network via the network interface for commanding the FPGA to load a bit configuration file from among the bit configuration files onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded bit configuration file, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded bit configuration file on the streaming data.

Intelligent data storage and processing using FPGA devices

Systems and methods are disclosed for routing of streaming data as between multiple compute resources. For example, the system may comprise a processor, a field programmable gate array (FPGA), a shared memory that is shared by a user space of an operating system for the processor and the FPGA, a network protocol stack, and driver code for execution by the processor. The driver code can be configured to (1) make the received streaming data available to a user mode software application for processing, (2) make data stored in the shared memory available to the FPGA via DMA transfers of data from the shared memory into the FPGA for processing thereby, (3) receive a stream of processed data from the FPGA, and (4) provide the received processed data to the network protocol stack for delivery to one or more data consumers. The shared memory can be accessible to the user mode for storing data produced by the user mode software application as a result of processing performed by the user mode software application on the streaming data received by the network protocol stack.

System and method for routing of streaming data as between multiple compute resources

Apparatuses and methods are disclosed for comparing a first biosequence string with a second biosequence string to assess similarity between those biosequence strings. For example, a field programmable gate array (FPGA) can be used to (1) detect substrings of the second biosequence string that are matches to substrings of the first biosequence string, and (2) map the detected substrings of the second biosequence string to corresponding positions in the first biosequence string where the detected substrings are located based on a data structure that links substrings of the first biosequence string to positions in the first biosequence string where the substrings of the first biosequence string are located. These operations can be used to seed an alignment between the first and second biosequence strings that permits comparisons to be performed over longer substrings of the first and second biosequence strings so that similarities between those longer substrings can be quantified.

Method and apparatus for performing similarity searching

Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a mapped variable field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.

A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and a plurality of hardware templates. The FPGA comprises configurable hardware logic, and the hardware templates define a plurality of different pipelined processing operations. The FPGA can be accessible over a network via the network interface for commanding the FPGA to load a hardware template from among the hardware templates onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded hardware template, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded hardware template on the streaming data.

A method and apparatus use hardware logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The hardware logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price.

Method and apparatus for processing financial information at hardware speeds using FPGA devices

A method for determining a concentration of a chemical of interest in a recirculating analyte system includes the steps of selecting a first indicator threshold, measuring the flow rate of the recirculating analyte system, controllably adding a known amount of reagent to the recirculating analyte system at an known flow rate, repetitively measuring an indicator of the recirculating analyte system downstream from the addition of the reagent, and computing the concentration of the chemical of interest of the recirculating analyte system when the indicator measurement crosses the indicator threshold.

Automated titration in a recirculating fluid system

A multi-functional data processing pipeline for use with machine learning is disclosed. The multi-functional pipeline may comprise a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations, and the pipelined data processing engines can include correlation logic. The multi-functional pipeline can be configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. In example embodiments, such pipelines can be used to accelerate convolutional layers in machine-learning technology such as convolutional neural networks.

Systems and methods are disclosed for routing of streaming data as between multiple compute resources. For example, the system may comprise a processor, a field programmable gate array (FPGA), a shared memory that is shared by a user space of an operating system for the processor and the FPGA, a network protocol stack, and driver code for execution by the processor. The driver code can be configured to (1) copy the streaming data received by the network protocol stack into the shared memory, (2) facilitate DMA transfers of the streaming data from the shared memory into the FPGA for processing thereby, (3) receive a stream of processed data from the FPGA, and (4) deliver the received processed data to the network protocol stack for delivery to one or more data consumers.

Methods and systems are disclosed where an FPGA offloads a plurality of processing tasks from a processor. The FPGA can process streaming data received via a network interface, and the FPGA can be controllable in response to control instructions received from the processor. The FPGA comprises resident hardware logic for a plurality of data processing engines that are combinable as a processing pipeline within the FPGA. In response to the control instructions, the FPGA can control which of the data processing engines are activated and which of the data processing engines are deactivated to selectively tap into the streaming data to perform pipelined processing operations on the streaming data via the activated data processing engines. The deactivated data processing engines remain on the FPGA and provide a pass through path for the streaming data whereby the deactivated data processing engines do not perform processing operations on streaming data received thereby.

Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.

Growing community of inventors

St. Louis, MO, United States of America

Roger Dean Chamberlain