Texas Instruments Corporation

Micron Technology Incorporated

Other

Roger D Norwood

Duy-Loan T Le

Kenneth A Poteet

Karl M Guttag

Wilbur Christian Vogley

Steven D Krueger

Anthony M Balistreri

Joseph H Neal

Joseph P Hartigan

Brian L Brown

David V Kersh, Iii

Terry R Lee

John Frederic Schreck

Brian M Shirley

Kallol Mazumder

Simon J Lovett

Jason M Brown

Cliff Zitlaw

Jimmie D Childers

Jeffrey Edward Koelling

Chitranjan N Reddy

Andrew M Love

Pravin P Patel

Derek R May

Ernest J Russell

Bharath Nagabhushanam

Brian W Huber

David R Brown

Michael C Stephens, Jr

Yutaka Komai

Mansour Fardad

Daniel B Penney

Jino Chun

Daniel B Penny

Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Apparatuses and methods for address detection

Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Asynchronous interface circuit and method for a pseudo-static memory device

Microelectronic devices having a protected input and methods for manufacturing such microelectronic devices. A microelectronic device has a microelectronic die and a support structure for coupling the die to voltage and signal sources. The microelectronic die can have integrated circuitry and a plurality of bond-pads coupled to the integrated circuitry. The bond-pads, for example, can include a reference voltage (Vref) bond-pad and a signal bond-pad adjacent to the Vref bond-pad. The signal bond-pad can be for a clock signal, a data signal, a strobe signal, an address signal, or another type signal for operating the integrated circuitry. The support structure can be a lead frame or a interposing substrate having a plurality of conductive members coupled to the bond-pads of the die. The conductive members can accordingly be metal pins in the case of lead frames or traces and solder ball-pads in the case of interposing substrates. Each conductive member can have a first end with a bond-site proximate to a corresponding bond-pad of the die, a second end defining an external connector, and an elongated conductive section connecting the bond-site to the external connector. The conductive members are generally arranged so that at least some of the bond-sites are arranged in a first row in which the bond-sites and a portion of the elongated sections are spaced apart from one other by a first gap width. The support structure can more specifically include a first conductive member having a first bond-site coupled to the Vref bond-pad by a first wire-bond line and a second conductive member having a second bond-site coupled to the signal bond-pad by a second wire-bond line. The first bond-site of the first conductive member can be spaced apart from the second bond-site of the second conductive member by a second gap width greater than the first gap width.

Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies

A DRAM memory device having two sets of power buses is provided. Each set includes a first bus having a first potential and a second bus having a second potential, both of which are required to activate a row of memory within a bank of memory. A first row is activated while it is connected to the first set of buses. If it is detected that the activation of a second row connected to the first set of buses will cause a power bump when it is time to deactivate the first row, the first row is switched over to the second set of buses prior to the activation of the second row. The first row can be precharged with the voltages from the second set of buses and the second row can be activated with the voltages from the first set of buses. Thus, the first row can be precharged without being adversely effected by the power bump on the first set of buses which improves the pause performance of the DRAM.

Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

High-speed memory arranged for operating synchronously with a

A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signal (*CLK) in response to the second logic state. The second clock signal has a frequency at least twice a frequency of the first clock signal. An address counter (221) is coupled to receive one of the first and second clock signals. The address counter produces a sequence of address signals corresponding to the one of the first and second clock signals. An array of memory cells is arranged to produce a sequence of data bits corresponding to the sequence of address signals. A logic circuit (235, 239, 240) is coupled to receive the sequence of data bits. The logic circuit produces a logical combination of the sequence of data bits.

Internal clock multiplication for test time reduction

A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal. The circuit may also include an OR logic circuit (310) coupled to the first and second clock signal output terminals, and a third pulse generator (312) coupled to the OR logic circuit, the third pulse generator having a third clock signal output terminal (314).

Clock skew circuit

High speed memory arranged for operating synchronously with a

Data processing system arranged for operating synchronously with a high

Testing of an integrated circuit having arrays of memory cells occurs by writing to all of the arrays at the same time. Normal writing occurs only to one array. Additional test data bus leads on the chip carry test data signals from selected arrays to comparison circuits. The outputs of the comparison circuits flow to the output circuits of the chip. This achieves writing test data to four times the number of arrays as in a normal write and reading test data from twice the number of arrays as in a normal read operation.

Memory access circuits for test time reduction

Random access memory with latency arranged for operating synchronously

Random access memory arranged for operating synchronously with a

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McKinney, TX, United States of America

Roger D Norwood