U.S. Philips Corporation

Nxp B.v.

Koninklijke Philips Corporation N.v.

Roger Cuppens

Anthonie Meindert Herman Ditewig

Cornelis D Hartgring

Franciscus Petrus Widdershoven

Marnix Claudius Vlot

Joannes J Koomen

Robertus D Verhaar

Louis Praamsma

Roelof Herman Willem Salters

Frans J List

Maurits Storms

Andrew J Walker

Guido J Dormans

Gerrit-Jan Hemink

Jan Middelhoek

Rutger C Wijburg

Robert H Beurze

Guido J M Dormans

Rob Verhaar

Alwin N Kronert

Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

Flash- and ROM-memory

The present invention relates to a voltage control circuit, semiconductor memory device, and method of controlling a voltage in a phase-change memory, wherein the voltage control circuit generates a controlled voltage which can be above the logic supply voltage. This voltage can limit the bit line voltage in a phase-change memory to allow the use of smaller transistors in the memory cells and in the program current part of the circuit. This results in smaller memory cells and modules.

Voltage control circuit for phase change memory

The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.

Current re-routing scheme for serial-programmed MRAM

A static memory cell comprising a pair of cross-coupled inverters () which is 'shadowed' with non-volatile memory elements () so that data written in the static memory can be stored in the non-volatile cell, but also can be recalled later. The non-volatile cells () are programmed with opposite data to increase the robustness of the retrieval process, and they are cross-coupled to the internal nodes (A, B) of the static memory cell, one the non-volatile cells () having a control gate connected to B and its source to A, and the other non-volatile element () having a control gate connected to A and its source to B. The drain of each non-volatile element () is connected by means of a respective pMOS transistor () to a program supply means.

Non-volatile static memory cell

An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.

MRAM-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference

The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

Method and circuit arrangement for memory error processing

The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row. Such matrix can be used in a read-while-write MRAM memory.

Magnetoresistive memory cell array and MRAM memory comprising such array

The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells. A method of reading a 2-transistor flash memory cellis provided. The memory cellcomprises a storage transistorwith a storage gateand a selecting transistorwith a select gate. The method comprises leaving the storage gatefloating while the select gateis switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage. A device according to the present invention comprises a switching circuit for leaving the storage gatefloating while the select gateis switched from the first voltage to the second voltage, the first voltage being lower than the second voltage.

Device and method to read a 2-transistor flash memory cell

The data processing circuit contains a non-volatile memory. Error correction is provided for computing individual correction data for correcting an error in an individual data unit in the non-volatile memory. The individual correction data is computed from a combination of a plurality of data units read from the non-volatile memory. A correction data store stores the individual correction data. Memory access is signaled to the correction data store, which outputs data corrected according to the correction data when said individual data unit is read. The circuit comprises error correction trigger means for triggering the error correction computing means to perform said computing independent of reading of the individual data from the non-volatile memory.

Data processing circuit with non-volatile memory and error correction circuitry

The threshold of a number of storage transistors is shifted in steps. After such a step, a collective current through the main current channels of a number of these storage transistors is sensed. The same gate-source voltage is applied to all these transistors during sensing. The collective current indicates whether the threshold of all transistors has been sufficiently shifted. If not, a further threshold shifting step is applied.

Circuit with non-volatile memory and method of erasing the memory a number of bits at a time

The invention relates to a non-volatile memory with floating gate, in particular a Flash-EPROM, in which writing takes place through injection of hot electrons into the floating gate and in which erasing takes place through injection of hot holes. To keep the write and erase voltages sufficiently low, p-type zones which locally increase the background doping concentration of the p-type substrate are provided around the n-type source and drain zones. These p-type zones cause an increased field strength at the drain zone whereby hot electrons are formed at the pinch-off point also at lower voltages. This increased background concentration in addition reduces the breakdown voltage of the pn junction of the source and drain zones, so that hot holes for erasing can be formed by pn breakdown at comparatively low voltages. The device is particularly suitable for being integrated into a signal processing IC manufactured in a standard process, such as a microcontroller.

Semiconductor device having a non-volatile memory and method of

The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.

Semiconductor device having an embedded non-volatile memory and method

A word oriented processing system includes a processing unit and a ferroelectric memory having a plurality of memory units organized in a matrix of rows and columns. Each memory unit stores a processor dataword of, for example, 8 or 16 bits, and contains a plurality of serial arrangements of, successively, a bitline connection, a first switching element, a ferroelectric capacitor and a node. The serial arrangements have the node in common. The node is connected to a plateline connection of the unit via second switching element. The processor reads or writes all bits of a word from one memory unit at a time. During reading or writing in one memory unit the first and second switching elements isolate the capacitors in other memory units from pulses on any of their plates.

Processing system with a ferroelectric memory

Each memory cell of an electrically-programmable semiconductor memory has a field-effect transistor with a charge-storage region. Efficient and fast injection of hot carriers into the charge-storage region is achieved by vertical punch-through of a depletion layer to a buried injector region, by application of programming voltages to a control gate and to the surface of the punch-through region. Non-injected carriers are removed via at least the transistor drain during the programming. A well-defined punch-through region can be obtained with a higher-doped boundary region at at least one side of the punch-through region to restrict the lateral spread of the depletion layer(s) and prevent parasitic connections. This permits closer spacing of the injector region to other regions of the memory cell, e.g. source and drain regions, and the injector region may adjoin an inset insulating field pattern. A compact cell array layout can be formed with a common connection region for the injector regions of two adjacent cells and for either a source or drain region of four other adjacent cells. The control gate and an erase gate may both be coupled in the same manner to the charge-storage region, and the cell can be operated with complementary voltage levels for writing and erasing. A feed-back mechanism with the start of injection from the punch-through and injector regions can provide a well-defined charge level limit for the erasure.

Electrically-programmable semiconductor memories with buried injector

The invention relates to an integrated circuit having a programmable cell, more particularly for use in an electronic card. The cell is provided with a programmable element (P) having two conductive layers (51, 52), which are separated from each other by a dielectric layer (53). The element can be programmed by applying between the layers 51, 52 a programming voltage such that an electric breakdown is produced in the dielectric layer (53), as a result of which the element passes permanently from an electrically non-conducting state to an electrically conducting state. According to the invention, the programmable cell comprises an asymmetric bistable trigger circuit (I,II). The trigger circuit (I,II) is loaded with the element (P) in such a manner that during operation it is in a first state if the element is electrically non-conducting and is in a second state if the element is electrically conducting.

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Eindhoven, Netherlands

Roger Cuppens