Sun Microsystems, Inc.

Oracle International Corporation

Roger Charles Mistely

Ali Vahidsafa

Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced.

Simultaneous transition testing of different clock domains in a digital integrated circuit

Methods and circuitry for processing a shadow scan instruction in a multi-threaded microprocessing environment include a bit sequence having a thread identifier, core identifiers and a shadow scan instruction. The core identifiers are assigned a state to identify microprocessor cores of a multi-core structure and are processed combinationally to determine if the shadow scan instruction is to be processed through a thread of the identified core. The processing of the shadow scan instruction through the thread of each of the identified cores is accomplished by a single load operation of the shadow scan instruction into the JTAG TAP controller.

Shadow scan decoder

An integrated circuit design block includes combinational and sequential logic defining core logic of the integrated circuit design block, and boundary logic defined at an outer region of the integrated circuit design block. The integrated circuit design block also includes a control test unit that has a scan chain decoder and a boundary scan decoder. The scan chain decoder includes scan chain select circuitry for enabling the scan chain decoder during scan testing of the core logic. The scan chain select circuitry further includes a pin for disabling the scan chain decoder during testing of the boundary logic. The scan chain decoder is limited to share pins defined by the boundary scan decoder, and is both 4-pin and 5-pin IEEE 1149.1 compliant.

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San Jose, CA, United States of America

Roger Charles Mistely