Stmicroelectronics Gmbh

Eidetic Communications Inc.

Roger Bertschmann

Sean Gregory Gibb

Saeid Sadeghi

Sean Gibb

Systems and methods are provided that facilitate performing hardware acceleration processes without utilizing specialized drivers that are software and hardware specific by controlling the hardware accelerator with NVMe commands. The NVMe commands may be based on standardized NVMe commands provided in the NVMe specification, or may be vendor-specific commands that are supported by the NVMe specification. The commands are sent to the NVMe accelerator by a host CPU which, in some embodiments, may be located remotely to the NVMe accelerator. The NVMe accelerator may include a CMB on which a host CPU may set up an NVMe queue in order to reduce PCIe traffic on a PCIe bus connecting the CPU and the NVMe accelerator. The CMB may also be used by a host CPU to transfer data for acceleration to reduce bandwidth in the DMA controller or to remove host staging buffers and memory copies.

Apparatus and method for controlling data acceleration

A clock control circuit for use in a multi-channel baud-rate timing recovery loop includes a control circuit responsive to a phase error signal from at least one phase detector for generating at least one clock control signal, wherein said control circuit propagates adjustments required for frequency correction in a synchronous fashion across all of the N-channels.

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Calgary, Canada

Roger Bertschmann