International Business Machines Corporation

Applied Materials, Inc.

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Adeia Semiconductor Bonding Technologies Inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Roger Allan Quon

Lawrence Alfred Clevenger

Christopher J Penny

Sivananda K Kanakasabapathy

Sean David Burns

Nicole A Saulnier

Matthew Earl Colburn

Chih-Chao Yang

Yann A M Mignot

Wei Wang

Terry Allen Spooner

Nelson M Felix

Kevin Shawn Petrarca

Tien-Jen Cheng

Jonathan H Griffith

David E Eichstadt

Sarah Huffsmith Knickerbocker

Kamalesh K Srivastava

Mukta G Farooq

Michael Rizzolo

Brian Christopher Sapp

Julie C Biggs

Carl John Radens

Theodorus E Standaert

Zhengwen O Li

Marc Adam Bergendahl

Cornelius Brown Peethala

Christopher Joseph Waskiewicz

Raghuveer Reddy Patlolla

Joseph R Johnson

James J Demarest

Randolph F Knarr

John Ulrich Knickerbocker

Benjamin David Briggs

Wolfgang Sauter

Koichi Motoyama

Hosadurga K Shobha

Richard Paul Volant

Griselda Bonilla

Subhash Laxman Shinde

James John Kelly

Stephan Grunow

William E Bernier

William Edward Sablinski

Atsushi Ogino

Marie S Cole

Lisa A Fanti

Raghav Sreenivasan

Anuja E DeSilva

Tasha E Lopez

David J Welsh

Jim S Liang

Stephen E Greco

Takashi Ando

Yun Yu Wang

Hemanth Jagannathan

Lars W Liebmann

Terence B Hook

Christian Lavoie

Michael Patrick Chudzik

Hsueh-Chung Chen

Wai-Kin Li

Xunyuan Zhang

Andrew Herbert Simon

Laertis Economikos

Mark Joseph Saly

Siddarth A Krishnan

Ahmet Serkan Ozcan

Emanuel Israel Cooper

Bhaskar Jyoti Bhuyan

Lan Yu

Kaushik Arun Kumar

Panayotis Constantinou Andricacos

Yiheng Xu

Chao-Kun Hu

Jin-Ping Han

Rainer Klaus Krause

H Bernhard Pogge

Rosemary A Previti-Kelly

Shawn Peter Fetterolf

Thomas Edward Lombardi

William Francis Landers

Todd Christopher Bailey

Paul Stephen McLaughlin

Shariq Siddiqui

Choongyeun Cho

Tyler Sherwood

Bernhard R Liegl

Andreas Scholze

Rohit Galatage

William John Durand

Keenan Navarre Woods

Keith Kwong-Hon Wong

Ryan Scott Smith

Hai Pham Longworth

Ryan P Deschner

Amirhasan Nourbakhsh

Raman Gaire

Jasvir Singh Jaspal

Han You

Embodiments of the present disclosure provide nanopore devices, such as nanopore sensors and/or other nanofluidic devices. In one or more embodiments, a nanopore device contains a substrate, an optional lower protective oxide layer disposed on the substrate, a membrane disposed on the lower protective oxide layer, and an optional upper protective oxide layer disposed on the membrane. The membrane has a pore and contains silicon nitride. The silicon nitride has a nitrogen to silicon ratio of about 0.98 to about 1.02 and the membrane has an intrinsic stress value of about &#x2212;1,000 MPa to about 1,000 MPa. The nanopore device also contains a channel extending through at least the substrate, the lower protective oxide layer, the membrane, the upper protective oxide layer, and the upper protective silicon nitride layer.

Nanofluidic device with silicon nitride membrane

Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

Power device structures and methods of making

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Self aligned pattern formation post spacer etchback in tight pitch configurations

Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.

Methods to fabricate dual pore devices

Nanopore flow cells and methods of manufacturing thereof are provided herein. In one embodiment a method of forming a flow cell includes forming a multi-layer stack on a first substrate, e.g., a monocrystalline silicon substrate, before transferring the multi-layer stack to a second substrate, e.g., a glass substrate. Here, the multi-layer stack features a membrane layer, having a first opening formed therethrough, where the membrane layer is disposed on the first substrate, and a material layer is disposed on the membrane layer. The method further includes patterning the second substrate to form a second opening therein and bonding the patterned surface of the second substrate to a surface of the multi-layer stack. The method further includes thinning the first substrate and thinning the second substrate. Here, the second substrate is thinned to where the second opening is disposed therethrough. The method further includes removing the thinned first substrate and at least portions of the material layer to expose opposite surfaces of the membrane layer.

Nanopore flow cells and methods of fabrication

A nitridation treatment method is provided. The nitridation treatment method includes executing a nitridation treatment with respect to a hydrophobic surface defining an interconnect trench to convert the hydrophobic surface to a hydrophilic surface. The nitridation treatment method further includes depositing a seed layer including a conductive material and manganese on the hydrophilic surface. The nitridation treatment method also includes thermally driving all the manganese out of the seed layer to form a diffusion barrier including manganese at the hydrophilic surface. In addition, the nitridation treatment method includes filling remaining space in the interconnect trench with the conductive material to form an interconnect.

Interconnect structure

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a &#x3b2; line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a &#x3b3; line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an &#x3b1; line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a &#x3b2;&#x3b3;&#x3b2; jog; a &#x3b2;&#x3b1;&#x3b2; jog; an &#x3b1;&#x3b2;&#x3b3; jog; a &#x3b3;&#x3b2;&#x3b1; jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.

Metallic synapses for neuromorphic and evolvable hardware

A method for back end of line (BEOL) integration for one or more interconnects includes forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric, forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers to remove portions of the diffusion barrier layer along the interlevel dielectric.

Back end of line integration for interconnects

A system for performing diffraction analysis, includes a mill for removing a surface portion of a sample, and an analyzer for performing diffraction analysis on the milled sample.

System and method for performing nano beam diffraction analysis

The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.

Metal insulator metal capacitor devices

A conductive interface includes a first conductor having a recessed area in least one surface. A dielectric layer has a trench positioned over the first conductor. A nitridized layer is formed on a top surface of the first conductor around the recessed area, to a depth on the first conductor that is shallower than a depth of the recessed area. A second conductor is formed in the trench and the recessed area to form a conductive contact with the first conductor.

Surface nitridation in metal interconnects

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a &#x3b2; line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a &#x3b3; line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an &#x3b1; line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a &#x3b2;&#x3b3;&#x3b2; jog; a &#x3b2;&#x3b1;&#x3b2; jog; and &#x3b1;&#x3b2;&#x3b3; jog; a &#x3b3;&#x3b2;&#x3b1; jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate microstructures of metallic interconnect structures. For example, an apparatus includes a single platform semiconductor processing chamber having first and second sub-chambers. The first sub-chamber is configured to receive a semiconductor substrate comprising a metallization layer formed on a dielectric layer, wherein a portion of the metallization layer is disposed within an opening etched in the dielectric layer, and to form a stress control layer on the metallization layer. The second sub-chamber comprises a programmable hot plate which is configured to perform a thermal anneal process to modulate a microstructure of the metallization layer while the stress control layer is disposed on the metallization layer, and without an air break between the process modules of forming the stress control layer and performing the thermal anneal process.

Modulating the microstructure of metallic interconnect structures

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Hopewell Junction, NY, United States of America

Roger Allan Quon