Motorola Corporation

Freescale Semiconductor,inc.

Roger Alan Smith

Mauricio Breternitz, Jr

Lucio F C Pessoa

Roman A Dyba

Perry P He

Katherine E Stewart

Farooq Butt

A communication system having an echo canceller is disclosed. One embodiment of the echo canceller includes an adaptive filter used to provide an estimate of reflected echo which is removed from the send signal. The echo canceller may also include a near-end talker signal detector which may be used to prevent the adaptive filter from adapting when a near-end talker signal is present. The echo canceller may also include a nonlinear processor used to further reduce any residual echo and to preserve background noise. The echo canceller may also include a monitor and control unit which may be used to monitor the filter coefficients and gain of the adaptive filter to maintain stability of the echo canceller, estimate pure delay, detect a tone, and inject a training signal. The echo canceller may also include a nonadaptive filter used to reduce the length of the adaptive filter.

Monitoring and control of an adaptive filter in a communication system

Method and apparatus for non-linear processing of an audio signal

Method of monitoring a secure encrypted communication, where the encryption key(s) is recovered by an escrow center having a master and multiple agents and the master receives the key encrypted using a mask scheme. Independent random masks are generated, which are then used to create dependent masks for each agent. The agents receive the mask information but no key information. The agents decide whether to allow the interception of an encrypted message. In response to the agents' decisions, the master is either enabled to recover the key or prevented from recovering the key. Encrypted key information is only available to the master. Multiple combinations of agents will provide sufficient information to the master to recover the key, avoiding the hold-out problems of the prior art. In one embodiment, multiple masters provide back-up protection when a master is unavailable.

Method for key escrow in a communication system and apparatus therefor

A method and apparatus for finding the hard-to-round double precision operands x when processed by a function f(x)and using these hard-to-round numbers to optimize f(x) hardware and software f(x) algorithms to ensure proper rounding begins by segmenting all proper x operands into analysis domains (FIG. ). The analysis domains are split into sub-domains ( ) where a linear generator is used to generate candidate hard-to-find values for each sub-domain ( ). A quadratic filter is used to reduce the list of candidates to a final list of hard-to-round values for f(x) ( ). The hard-to-round double precision values are used to set a precision of hardware or software f(x) algorithm to ensure proper rounding or all valid x operations while simultaneously ensuring that too much precision, and therefore, reduced performance, is avoided.

Method and apparatus for producing correctly rounded values of functions using double precision operands

During a compressing portion, memory ( ) is divided into cache line blocks ( ). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks ( ) are stored in a memory ( ). During a decompression portion, a cache line ( ) is accessed based on an instruction pointer ( ) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer ( ) value.

Method and apparatus for data compression and decompression for a data processor system

A compiler ( ) constructs (FIGS. ) a Reduced Flowgraph (RFG) from computer source code ( ). The RFG is used to instrument (FIG. ) code ( ). An object module is created ( ) and executed ( ). Resulting path frequency counts are written to a counts file ( ). A compiler ( ) uses the source code ( ) and the generated counts to identify runtime correlations between successive path edges and Superedges. An object module ( ) is generated containing reordered ( ) code generated to optimize performance based on the runtime correlations. If cloning is enabled ( ), high frequency path edges are cloned ( ) or duplicated to minimize cross edge branching.

Method and apparatus for hierarchical restructuring of computer code

Method and apparatus for compression, decompression, and execution of program code

During a compressing portion, memory (,) is divided into cache line blocks (,). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (,) are stored in a memory (,). During a decompression portion, a cache line (,) is accessed based on an instruction pointer (,) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (,) value.

Two related extended precision operand formats provide for efficient multiply/accumulate operations in a SIMD data processing system. Each format utilizes a group of &ldquo;b&rdquo; bit elements in a vector register. Each of the elements provides &ldquo;m&rdquo; bits of precision, with b>m. The remaining b&minus;m bits in each element accumulate overflows and carries across multiple additions and subtractions. Existing SIMD multiply-sum instructions can be used to efficiently take input operands from the first format and produce output results in the second extended precision format when b,&equals;2b,and m,&equals;2m,.

SIMD data processing extended precision arithmetic operand format

One way of filtering graphics images to remove pixel dropout and shot noise while preserving overall image quality is to use non-linear filters based on rank order of an M.times.N grid of pixel values surrounding a pixel to be filtered. This rank order filter method for M.times.N grids first sorts columns, then sorts rows, and finally sorts diagonals to obtain either just a median filter value, a rank-based filter value, or a complete sorted order of the M.times.N grid. All of the sort operations are control-flow-free allowing implementation on SIMD processors processing multiple overlapping M.times.N grids in parallel. Advantage is taken of columns and rows that are shared among the horizontally and vertically overlapping M.times.N grids in the digital image to reduce the total number of sort operations for the image.

SIMD computation of rank based filters for M.times.N grids

A floating point unit (60) capable of executing projection instructions provides performance improvement in multiple precision floating point arithmetic. The projection instructions provide for obtaining partial sequences of numbers, products, and sums which have definite alignments and widths which a programmer can set. This allows very fast computation of both individual intermediate computations and final results. A range projection instruction (210, 410) builds a mask with an exponent from one source (230, 430) and a mantissa from another (240, 440). A project instruction (610) builds a result by masking (660) mantissa bits in a source operand after alignment (630) with a mask. Projection multiply (810), add (1000), and subtract instructions build results by masking (850, 1070) mantissa bits of unrounded partial results after alignment (830, 1020, 1040) with a mask.

Method and apparatus for implementing floating point projection

A method for multiple context analysis of software applications in a multiprocessing (22, 23), multithreaded computer environment utilizes instrumentation code inserted (54, 55) into the applications. For each execution (67) of the application (60), a context set is selected (62). Execution of the instrumented code (67) provides information for analysis in an instrumentation buffer (82) addressed by a reserved register (80) or buffer pointer. The operating system is responsible for providing in the reserved register (80) the address of the instrumentation buffer (82) appropriate for each instrumented context executed. When the application (60) is done with an instrumentation buffer (82), the buffer may be processed by filter software (68). The combination of using a reserved register (80) and allowing the operating system to keep track of relevant context switches allows applications to be instrumented (54, 55) for various context sets without the necessity of modifying (53) or recompiling (52) the application software (60).

Multiple context software analysis

A method and apparatus for sequencing computer instructions in memory (24) to provide for more instruction efficient execution by a central processing unit (CPU) (22) begins by executing the computer instructions via the CPU (22) and creating a trace file (FIG. 2) in memory (24). The trace file is then scanned using a window size greater than two (i.e., more than two instructions or basic blocks/ groups of instructions are selected as each window) and correlations are determined between several pairs of instructions in each window (FIGS. 9 and 10). The correlations obtained by the window procedure are then analyzed (FIG. 11) to determine an efficient ordering of computer instructions for subsequent execution by any target CPU.

Method and apparatus for sequencing computer instruction execution in a

A native microprocessor (20) accesses a foreign block of computer code. An initial block scope defining translation parameters is assigned to the block (106). The block of 'foreign' code is translated to 'native' code (108). An optimization efficiency is calculated for the translated block (110). A rescheduling criterion is established based on the optimization efficiency (112). The block of native code is executed (114). On subsequent accesses of the block when the reschedule criterion is met (116) the block scope is redefined (118).

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Austin, TX, United States of America

Roger Alan Smith