Exar Corporation

Micro Power Systems, Inc.

Xicor Corporation

Roger A Levinson

John M Caruso

Ali Tasdighi

Quoi V Huynh

Phillip J Benzel

Xiaole Chen

Sang T Ngo

Methods and apparatus for converting analog signals to digital signals using a switched integrator. A method includes receiving the analog signal at a summing junction, receiving a clock signal transitioning between a first level and a second level, connecting an output of the summing junction to an integrator when the clock signal is at the first level, and disconnecting the output of the summing junction from the integrator when the clock signal is at the second level. An output signal is provided, and is determined by the polarity of an output of the integrator when the clock signal transitions from the first level to the second level. The output signal is delayed, and received with a digital-to-analog converter; which provides an output to the summing junction.

Analog-to-digital converter with switched integrator

A soft clipper circuit in CMOS technology not only allows the knee to be programmed, but also the slope of the curve after the knee to be programmed. This is accomplished by putting a second transconductance in parallel with the first transconductance, and using a switching circuit to connect the output of the second transconductance to that of the first transconductance when the knee level is reached. This is determined by a comparator which has an input coupled to the second transconductance and controls a control node of the switching circuit.

CMOS soft clipper

An MOS FET circuit with a summing circuit at the input of an amplifier to provide charge cancellation. The summing circuit is capacitively coupled to the input with a charge cancellation capacitor. A separate amplifier, having components substantially the same as the components of the first amplifier, is connected through the charge cancellation capacitor to the first amplifier.

Charge injection cancellation technique

Method and circuitry for power control in integrated circuits using field effect transistor (FET) technology are disclosed. According to the present invention, for each circuit block that is biased by the power supply voltage a dedicated level shifter is inserted between the block and the power supply. In one embodiment, a switch is also coupled in parallel to the level shifter. The switch is closed when a low external power supply voltage is applied, and opened when a higher power supply voltage is applied. A second embodiment removes the switch and adds a bias generator that supplies a bias voltage to each level shifter.

Power supply control techniques for FET circuits

A reference voltage generating method and circuit is disclosed where the output can be programmably calibrated for minimum temperature drift. Output calibration is performed by adjusting a value of resistance of a resistor in a band-gap circuit. Digitally programmable switches are used to incrementally reduce or increase the value of the target resistor. The control circuit according to the present invention is also designed such that it tracks variations in process and temperature.

Programmable low drift reference voltage generator

Various innovative circuit techniques that make possible a single chip, cost effective implementation of a CCD signal digitizing circuit are disclosed. Among the various features of the single chip digitizing circuit is the use of a single clock to sample the CCD signal and to digitize the analog signal. By providing a tight control over the minimum required settling time delay at the input of the analog to digital converter (ADC), the speed of the circuit is optimized. Other features include support for various modes of CCD operations, reference voltage feedback from ADC to sampling circuit to compensate for offset voltage, dual register serial input/output circuit, and multiplexed ADC input.

CCD signal digitizing integrated circuit

A current driven span voltage source for use in an analog to digital converter includes a zero reference resistor serially connected with a resistor ladder. A first current source selectively passes a part of a first current through the resistor ladder to establish a span (gain) voltage range, and a second current source selectively passes a part of a second current through the zero reference resistor to establish a zero reference voltage for the span voltage range. The controlled current sources increase speed, reduce power and thermal noise, and improve temperature related performance as compared with voltage driven span and reference sources using operational amplifiers.

Analog-digital converter using current controlled voltage reference

A pipelined analog to digital converter in which data samples ripple down through the pipeline of comparator stages. Each stage of the pipeline includes switch capacitor amplifiers for comparing an analog signal to a first reference voltage, to a second reference voltage, and to an average of the first and second reference voltages. Fan out of circuit components can be eliminated in succeeding stages, and error correction is provided by including overlapping of ranges passed by an earlier stage to a subsequent stage.

Pipelined analog to digital converter

A digital to analog converter employs an operational amplifier as an active summing device for summing a first analog voltage corresponding to most significant bits of a digital value and a second analog voltage corresponding to least significant bits of the digital value. In a multi-channel application, a single MSB DAC can be shared by all channels through first MUXs in each channel with each channel having an independent LSB DAC. Alternatively, a single LSB DAC can be shared by all channels through second MUXs in each channel. Gain of the voltage summing operational amplifier in each channel is determined by values of a resistor connecting the output of the LSB DAC to the inverting negative input of the operational amplifier and of a feedback resistor connecting the amplifier output to the inverting negative input.

Multi-channel digital to analog converter

A digital to analog converter (DAC) incorporates a novel subranging voltage output DAC that delivers high multiplying bandwidth while consuming low power and requires small silicon area. The higher order digital input bits (MSBS) select a voltage range (VMSB) from a first resistor divider DAC network. The VMSB is then applied to the input of a small high speed low power differential input single ended output LSB programmable attenuator amplifier. Transistor follower devices effectively buffer the MSB section to the LSB section and increase bandwidth and speed of operation as well as permitting multichannel sharing of a single precision MSB voltage divider network.

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San Francisco, CA, United States of America

Roger A Levinson