Intel Corporation

Institute for the Development of Emerging Architectures, L.l.c.

Idea Corporation

Roger A Golliver

Shreekant S Thakkar

Gilbert A Neiger

Francis X Mckeen

James A Sutton, Ii

Howard C Herbert

Derrick Chu Lin

Carl M Ellison

Ken Reneris

Millind Mittal

Gautam B Doshi

Michael R Greenfield

Jerome C Huck

Alan Hersh Karp

Michael J Morrison

Glenn T Colon-Bonet

Sivakumar Makineni

Peter Markstein

Carole Dulong

Sridhar Samudrala

Jeff Wiedemeier

Guillermo Juan Rozas

David W Grawrock

Harshvardhan P Sharangpani

Milland Mittal

Sunnhyuk Kimn

Subramaniam M Maiyuran

Dale Calvin Morris

Eric W Mahurin

Vladimir M Pentkovski

Lance E Hacking

Salvador Palanca

Thomas R Huff

Glen Colon-Bonet

Mike Morrison

Guatam Bhawandas Doshi

Bob Norin

Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.

Methods and apparatus to manage workload memory allocation

Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example apparatus includes a workload controller to log instances of access to data records in a log, the workload controller to identify, from the log, a first set of the data records to be migrated to a first memory and a second set of the data records to be migrated to a second memory based on frequencies at which the data records were accessed during a runtime, and a memory manager to migrate the first set of data records to the first memory, and migrate the second set of data records to the second memory.

A computer-implemented method and a corresponding computer system for emulation of Extended Memory Semantics (EMS) operations. The method and system include obtaining a set of computer instructions that include an EMS operation, converting the EMS operation into a corresponding atomic memory operation (AMO), and executing the AMO on at least one processor of a computer.

Providing extended memory semantics with atomic memory operations

A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.

Vector logical reduction operation implemented using swizzling on a semiconductor chip

A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.

Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation

A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

Functional unit for vector integer multiply add instruction

A processing system has a processor that can operate in a normal ringoperating mode and one or more higher ring operating modes above the normal ringoperating mode. In addition, the processor can operate in an isolated execution mode. A memory in the processing system may include an ordinary memory area that can be accessed from the normal ringoperating mode, as well as an isolated memory area that can be accessed from the isolated execution mode but not from the normal ringoperating mode. The processing system may also include an operating system (OS) nub, as well as a key generator. The key generator may generate an OS nub key (OSNK) based at least in part on an identification of the OS nub and a master binding key (BK) of the platform. Other embodiments are described and claimed.

Protecting software environment in isolated execution

In one embodiment, a method of attestation involves a special mode of operation. The method comprises storing an audit log within protected memory of a platform. The audit log is a listing of data representing one or more software modules loaded into the platform. The audit log is retrieved from the protected memory in response to receiving an attestation request. Then, the retrieved audit log is digitally signed to produce a digital signature in response to the attestation request.

Platform and method for remote attestation of a platform

In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.

Attestation key memory device and bus

Growing community of inventors

Beaverton, OR, United States of America

Roger A Golliver