Texas Instruments Corporation

Roger A Cline

Charvaka Duvvury

Bernhard H Andresen

Kyle Clifton Schulmeyer

Ponnarith Pok

Craig Thomas Salling

Jorge Salcedo-Suner

Jose A Cadena-Hernandez

Bernhard H Adresen

A circuit for protecting against electrostatic discharge events has a semiconductor substrate () of first conductivity embedding a first diode in a well () of opposite second conductivity, the diode's anode () tied to an I/O pin-to-be-protected () at a first voltage, and the first diode's cathode () connected to the first drain () of a first MOS transistor in the substrate. The first MOS transistor's first gate () is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain () merged with the first source of the first MOS transistor, and its second source (), together with its second gate (), tied to ground potential ().

Electrostatic discharge protection device for high voltage

An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

ESD protection using diode-isolated gate-grounded nMOS with diode string

ESD protection using diode-isolated gate-grounded NMOS with diode string

The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.

Design implementation to suppress latchup in voltage tolerant circuits

Protection circuitry () for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry () includes a discharge circuitry () on a substrate () that discharges an ESD pulse to the integrated circuit to ground (). The protection circuitry () also includes a drive circuitry () that uses a portion of the ESD pulse voltage to bias the substrate () using a first guard ring () in the substrate (), which surrounds the discharge circuitry () and drive circuitry (). The protection circuitry () further includes a second guard ring () in substrate (), which surrounds the first guard ring () and connects to Vss/ground potential (), thereby providing uniformity of the substrate bias.

ESD protection with uniform substrate bias

An output circuit for improved ESD protection (FIG. ) comprising a pMOS pull-up output transistor connected between a signal (I/O) pad and Vdd power supply , the pull-up transistor located in a n-well and having at least one gate , the gate connected to internal circuitry . A dummy pMOS transistor connected in parallel with the pull-up transistor, the dummy transistor also located in the n-well , whereby both the pull-up transistor and the dummy transistor participate in protection against an ESD event. The dummy transistor having at least one gate , this gate connected through a resistor to the Vdd power supply . The n-well connected to the Vdd power supply

Output buffer and I/O protection circuit for CMOS technology

An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry ( ) associated with each signal pad. The integrated circuit has internal circuitry ( ) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits ( ) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P N P ) that are biased during normal operation so that electrical over-stress does not occur.

Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process

An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry ( ) associated with each signal pad. The integrated circuit has internal circuitry ( ) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits ( ) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P , N , P ) that are biased during normal operation so that electrical over-stress does not occur.

An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (,) which uses low voltage transistors (N,N,) to provide protection to a signal pad that handles high voltage signals during normal operation of the integrated circuit. The external signal is operable at a second supply voltage that is higher than the Vdd supply voltage. The internal circuitry of the integrated circuit is comprised of MOS transistors that have gate oxide of a first thickness that has a V,suitable for the Vdd supply voltage but not for the second supply voltage. The ESD protection transistors use the same gate oxide thickness as the MOS transistors used in the internal circuitry. A substrate region in the semiconductor substrate is enclosed by a highly doped region (,) so that the back-gates of the ESD protection transistors can be voltage pumped by pump circuitry (,) in order to trigger bipolar conduction of the ESD protection transistors at a lower voltage. Control circuitry (,) is connected to the signal bond pad and to gates of the ESD protection transistors and to gates of the pump transistors to provide a voltage pulse to each gate in response to an ESD zap applied to the signal bond pad. The control circuitry provides a bias potential to the gates of the ESD protection transistors and pump transistors such that the maximum operating voltage of the gate oxide of each device is not exceeded during normal operation of the integrated circuit, thereby avoiding electrical over-stress (EOS) of the low voltage devices in the ESD protection circuitry.

NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors

An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) A substrate region in the semiconductor substrate is enclosed by a ring of highly doped region (350). An NMOS ESD protection transistor (N1) with its backgate in the enclosed substrate region can be voltage pumped by pump circuitry (N2) in order to trigger bipolar conduction of the ESD protection transistor at a lower voltage. Control circuitry (304) is connected to the signal bond pad and to the gate of amplifier circuitry (P1) to provide a voltage pulse in response to an ESD zap applied to the signal bond pad. PMOS amplifier circuitry (P1) provides an amplified voltage pulse to the pump circuitry with a magnitude approximately equal to the ESD potential on the signal pad so that a strong pump current is provided to the highly doped ring.

CMOS triggered NMOS ESD protection circuit

An autoranging digital/analog (D/A) phase locked loop (PLL) 10 includes a frequency discriminator circuit 12 connected to a shift register 14. Shift register 14 is connected to a voltage controlled oscillator circuit (VCO) 16. VCO 16 is connected to generic counter 17. Counter 17 is optional in this preferred embodiment. Counter 17 is connected to a phase detector 13 and frequency discriminator 12. Phase detector 13 is connected to a charge pump control circuit 15. Charge pump control circuit 15 is also connected to VCO 16. A second generic counter 11 is connected to frequency discriminator 12. Second counter 11 is also optional in this preferred embodiment. First generic counter 17 and second generic counter 11 can be implemented to reduce the phase detector frequency relative to VCO 16 or a reference clock signal frequency. Ratios of M to N allow frequency multiplication or division of VCO 16 relative to the reference clock signal frequency. A method for achieving phase lock between a first signal and a second signal, in accordance with the present invention, comprises the steps of comparing the phases of the first signal and the second signal, adjusting the frequency of the second signal in a digital fashion until the phases of the first signal and second signal are within a predetermined phase relationship; and adjusting the frequency of the second signal in an analog fashion until a phase lock is obtained between the first signal and the second signal.

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Plano, TX, United States of America

Roger A Cline