Hewlett-packard Development Company, L.p.

Psemi Corporation

Rogelio Cicili

Eric T Martin

James Michael Gardner

James Richard Przybyla

Daryl E Anderson

Scott A Linn

Garrett E Clark

Vincent C Korthuis

Gary G Lutnesky

Donald J Milligan

Tsuyoshi Yamashita

Sirena Chi Lu

Jeremy Spencer

Sirena Lu

Methods and devices for a cascode differential input pair with low headroom voltage and high output impedance are presented. The cascode differential input pair includes first and second input (cascode) stages, each including a common-source regular transistor in series connection with a common-gate intrinsic transistor. Sources of the regular transistors are tied, and gates of the intrinsic transistors are tied. A gate voltage to the intrinsic transistors is provided by a source voltage at the sources of the regular transistors, the source voltage based on a common mode input voltage of the cascode differential input pair. According to one aspect, the cascode differential input pair is part of a differential amplifier that includes a current source coupled to the sources of the regular transistors, and a load coupled to drains of the intrinsic transistors.

Intrinsic MOS cascode differential input pair

An integrated circuit includes a plurality of fluid actuation devices, a plurality of memory cells, a high-voltage high-power supply node, and a high-voltage low-power supply node. The high-voltage high-power supply node is to supply a first voltage and a first maximum current to the plurality of fluid actuation devices. The high-voltage low-power supply node is to supply a second voltage and a second maximum current to the plurality of memory cells.

Integrated circuits including high-voltage high-power and high-voltage low-power supply nodes

A fluidic die includes fluid-transfer elements, and a temperature sensor to monitor a temperature on the fluidic die. The fluidic die includes a trickle-warming circuit to warm fluid transferrable by the fluid-transfer elements, and a pulse-warming circuit to warm the fluid. A warming control circuit selectively activates the trickle-warming and pulse-warming circuits.

Fluidic die having trickle-warming and pulse-warming circuits

Methods and devices for a wide-swing cascode current mirror with low headroom voltage and high output impedance are presented. An input leg of the current mirror includes a composite transistor in series connection with an intrinsic transistor. The composite transistor includes two series-connected regular transistors with respective sizes that are twice the size of the intrinsic transistor. An output leg of the current mirror includes a regular transistor in series connection with an intrinsic transistor. A gate voltage of the composite transistor, provided at a node that is common to gates of the two series-connected regular transistors, self-establishes when a reference current flows through the input leg. The self-established gate voltage is used to bias the regular transistor of the output leg. Biasing voltages to gates of the intrinsic transistors is provided by an intermediate node that provides the series connection of the regular transistors of the composite transistor.

Wide-swing intrinsic MOSFET cascode current mirror

In one example in accordance with the present disclosure, a fluidic die is described. The fluidic die includes a substrate and fluid actuators, the fluid actuators being disposed on the substrate. The fluidic die also includes a bond pad region defined on the substrate. The bond pad region includes a high aspect ratio power delivery bond pad with multiple bonding sites and a high aspect ratio power return bond pad with multiple bonding sites.

Fluidic die with high aspect ratio power bond pads

Examples include a fluidic die. The fluidic die comprises an array of field effect transistors including field effect transistors of a first size and field effect transistors of a second size. At least one connecting member interconnects at least some of the field effect transistors of the array of field effect transistors. The fluidic die further comprises a first fluid actuator connected to a first set of field effect transistors having at least one field effect transistor of the first size. The die includes a second fluid actuator connected to a second respective set of field effect transistors having a first respective field effect transistor of the second size interconnected to at least one other field effect transistor of the array.

Connected field effect transistors

In various examples, a fluid ejection device may include a substrate with a fluid feed hole and a corrosion-detecting conductive path or sensor disposed behind a wall of the fluid feed hold. The corrosion-detecting conductive path or sensor may close a circuit in response being exposed to a fluid contained within the fluid feed hole.

Fluid feed hole corrosion detection

Examples include a fluidic die. The fluidic die comprises an array of field effect transistors. Connecting members electrically connect at least some of the field effect transistors of the array of field effect transistors, and the field effect transistors of the array are arranged into respective sets of field effect transistors. The fluidic die further comprises a first fluid actuator connected to a first set of field effect transistors having a first number of field effect transistors. The die includes a second fluid actuator connected to a second respective set of field effect transistors having a second number of field effect transistors that is different than the first number of field effect transistors.

Fluid actuators connected to field effect transistors

A logic circuitry package for a replaceable print apparatus component comprises at least one logic circuit and an interface to communicate with a print apparatus logic circuit. The at least one logic circuit is configured to receive, via the interface, calibration parameters including an offset parameter and a sensor ID. The at least one logic circuit is configured to output, via the interface, a digital value corresponding to the sensor ID and offset based on the offset parameter.

Logic circuitry package

A fluidic die including fluid chambers, each including an electrode exposed to an interior of the fluid chamber and each having a corresponding fluid actuator operating at a first voltage level. Monitoring circuitry, operating at a second voltage level lower than the first voltage level, includes a select transistor and a pulldown transistor for each fluid chamber to selectively couple to the electrode, at least the select transistor being a high voltage tolerant transistor to operate at the second voltage in a normal operating condition and having a breakdown voltage level greater than the first voltage level to prevent a fault current from flowing into the select transistor from the electrode in a fault condition if the fluid actuator short-circuits to the electrode.

Fluidic die with low voltage monitoring circuit including high voltage tolerant transistor

Example implementations relate to current leakage testing of a fluid ejection die. For example, a fluid ejection die may include plurality of nozzles, each nozzle among the plurality of nozzles including a nozzle sensor and a fluid ejector. The plurality of nozzle sensors may comprise a first subset and a second subset, each nozzle sensor among the plurality of nozzle sensors of the first subset may be electrically coupled to a first control line by a respective switch among a first group of switches, and each nozzle sensor among the plurality of nozzle sensors of the second subset may be electrically coupled to a second control line by a respective switch among a second group of switches. The fluid ejection die may include a control circuit to perform a current leakage test of the plurality of nozzles using the first control line and the second control line.

Current leakage test of a fluid ejection die

A fluidic die includes a sense architecture having a global sense block to provide an analog reference signal and an array of distributed sense blocks. Each distributed sense block is to receive a same set of addresses via an address bus and each is to receive a corresponding sense enable signal having an enable value or a disable value. Each distributed sense block includes an array of sensors, each sensor corresponding to a different address of the set of addresses and a sample circuit to apply the analog reference signal to the sensor corresponding to the address on the address bus when the corresponding sense enable signal has the enable value, and provide to the global sense block an analog sense signal from the sensor resulting from application of the analog reference signal.

Fluidic die sense architecture

In one example in accordance with the present disclosure, a fluid ejection device is described. The fluid ejection device includes a number of nozzles to eject an amount of fluid. A first field-effect transistor (FET) activates a first fluidic operation component and a second FET activates a second fluidic operation component. The first FET and the second FET are selected from among a high-side switch FET, a low-side switch FET, and a hybrid FET and the first FET and the second FET are different from one another.

Growing community of inventors

Corvallis, OR, United States of America

Rogelio Cicili