Schlumberger Technology Corporation

Schlumberger Technologies, Inc.

Nptest, Inc.

Rodolfo F Garcia

Egbert Graeve

A method and associated apparatus for testing devices outputting source synchronous signals using automated test equipment (&ldquo;ATE&rdquo;). An output data signal and an output clock signal from such a source synchronous device under test are delayed using a delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.

Test method and apparatus for source synchronous signals

A test system, for testing circuits, having two operating modes, a normal mode and an accelerated mode. The test system has a first start memory, a second start memory, a first sequence memory, and a second sequence memory. The start memories provide sequence memory addresses for addressing the sequence memories, and the sequence memories provide event sequences in response to sequence memory addresses. If operating in normal mode, the start memories are electronically coupled (switched) to provide a single sequence memory address to both sequence memories. If operating in accelerated mode, the start memories are electronically coupled so that the first start memory provides a first sequence memory address to the first sequence memory and the second start memory provides an independent second sequence memory address to the second sequence memory. In particular embodiments, the first and second start memories are of the same size, the first and second sequence memories are of the same size, and the sequence memories produce a word including at least two events in response to a sequence memory address. In a further embodiment, the test system has three operating modes: normal, accelerated, and double-accelerated. For the double-accelerated mode, four start memories and four sequence memories are provided.

Accelerated mode tester timing

A Device Under Test ('DUT') is monitored to determine when a test stops due to failure, completion, or otherwise. A series of signal stimulus in the form of a maintain active signal are applied to the DUT after the test has stopped. This protects devices that need continuous functional stimulus while connected to a power source. Upon the resumption of the test, the maintain active signal stimulus is synchronously replaced with an input test signal stimulus.

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San Jose, CA, United States of America

Rodolfo F Garcia