Qualcomm Incorporated

Atlazo, Inc.

Rodolfo Beraha

Amin Ansari

Javid Jaffari

Dilip Krishnaswamy

Jeffrey Alexander Levin

Venkat Rangan

Karim Arabi

Vito Remo Bica

Kishore Yalamanchili

Rashmi Keshava Iyengar

Yogeshwar Narayanan Nagaraj

Disclosed are methods, apparatus and systems for a binary neural network accelerator engine. One example circuit is designed to perform a multiply-and-accumulate (MAC) operation using logic circuits that include a first set of exclusive nor (XNOR) gates to generate a product vector based on a bit-wise XNOR operation two vectors. The result is folded and operated on by another set of logic circuits that provide an output for a series of adder circuits. The MAC circuit can be implemented as part of binary neural network at a small footprint to effect power and cost savings.

Binary neural network accelerator engine methods and systems

Systems and methods are disclosed for a hybrid parallel-serial memory access by a system on chip (SoC). The SoC is electrically coupled to the memory by both a parallel access channel and a separate serial access channel. A request for access to the memory is received. In response to receiving the request to access the memory, a type of memory access is identified. A determination is then made whether to access the memory with the serial access channel. In response to the determination to access the memory with the serial access channel, a first portion of the memory is accessed with the parallel access channel, and a second portion of the memory is accessed with the serial access channel.

Systems and methods for a hybrid parallel-serial memory access

Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC.

Statistics and failure detection in a network on a chip (NoC) network

Adaptive hardware reconfiguration of configurable co-processor cores for hardware optimization of functionality blocks based on use case prediction, and related methods, circuits, and computer-readable media are disclosed. In one embodiment, an indication of one or more applications for possible execution is received. Execution probabilities for respective ones of the one or more applications are received. One or more mappings of the one or more applications to one or more functionality blocks is accessed, and a net benefit of hardware reconfiguration of one or more configurable co-processor cores of a multicore central processing unit for the one or more functionality blocks is calculated based on the execution probabilities and the mappings. An optimal hardware reconfiguration is determined based on a current hardware configuration and the calculated net benefit. The configurable co-processor cores are reconfigured based on the optimal hardware reconfiguration.

Adaptive hardware reconfiguration of configurable co-processor cores for hardware optimization of functionality blocks based on use case prediction, and related methods, circuits, and computer-readable media

Lempel-Ziv (LZ)-based data compression employing implicit variable-length distance coding is disclosed. Distances in LZ-based data compression length and distance blocks are implicit variable-length encoded during data compression to avoid padding encoded distances with extra bits (e.g., trailing 0's) that require fewer bits for storage than the number of bits needed to store maximum distance length. This reduces distance bit lengths in compressed output data to further reduce data size. During data compression, a distance table is generated that contains entries each having an assigned base and a number of extra bits to be read in compressed data during data decompression. In this manner, during data decompression, the entries in the distance table can be consulted to determine the number of bits in the variable-encoded distance in the compressed data to be read since the encoded distances can be encoded in the compressed data in fewer bits and without bit padding.

Growing community of inventors

San Diego, CA, United States of America

Rodolfo Beraha