Qualcomm Incorporated

Microsoft Technology Licensing, LLC

International Business Machines Corporation

Other

Qualcomm Connected Experience, Inc.

Rodney Wayne Smith

Thomas Andrew Sartorius

James Norris Dieffenderfer

Brian Stempel

Jeffrey Todd Bridges

Michael Scott McIlvaine

Shivam Priyadarshi

Yusuf Cagatay Tekmen

Thomas Philip Speier

Victor Roberts Augsburg

Vignyan Reddy Kothinti Naresh

Kiran Ravi Seth

Anil Krishna

Daren Eugene Streett

Melinda Joyce Brown

Raguram Damodaran

Michael W Morrow

Kenneth Alan Dockser

Gagan Gupta

Jeffery Michael Schottmiller

Andrew S Irwin

Ryan Donovan Wells

Rami Mohammad Al Sheikh

Norman S Gargash

David Tennyson Harper, Iii

Luke Yen

Robert Douglas Clancy

Arthur Perais

Sandeep Suresh Navada

Douglas Christopher Burger

Ajamu Akinwunmi Wesley

Manish Garg

Derek W Carr

Nabil A Rizk

Richard Alan Moore

Ronny A Pena

Nathan Samuel Nunamaker

Robert L Goldiez

Leslie Mark DeBruyne

Peter P Eacmen

Kevin Allen Sapp

Stephen G Geist

Pritha Ghoshal

William M Markham

Michael Egnoah Birenbach

Les Mark DeBruyne

Raghavan Madhavan

Niket Kumar Choudhary

David John Mandzak

Tejaswi Talluru

Kevin Charles Burke

Daniel Higdon

Serena Badran-Louca

Gregory Lee Brookshire

Harsh Thakker

Kevin Jaget

Sang Hoon Lee

Walter W Robinson

Michael S Mcilvaine

Jeffrey M Schottmiller

Michael Scott Mcilvaine

Brian Michael Stempel

Michael William Morrow

Daniel S Higdon

Kulin Narendra Kothari

Brian M Stempel

David J Mandzak

Victor Robert Augsburg

Kenneth Alan c/o Qualcomm Incorporated Dockser

Nabil Amir Rizk

Brian Micheal Stempel

Michael Scott Mcllvaine

Leslie Mark Debruyne

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

A reach matrix scheduler circuit for scheduling instructions to be executed in a processor is disclosed. The scheduler circuit includes an N&#xd7;R matrix wake-up circuit, where 'N' is the instruction window size of the scheduler circuit, and 'R' is the 'reach' within the instruction window of the matrix wake-up circuit, with &#x2018;R&#x2019; being less than &#x2018;N&#x2019;. A grant line associated with each instruction request entry in the N&#xd7;R matrix wake-up circuit is coupled to &#x2018;R&#x2019; other instruction entries among the &#x2018;N&#x2019; instruction entries. When a producer instruction in an instruction request entry is ready for issuance, the grant line associated with the instruction request entry is activated so that any other instruction entries coupled to the grant line (i.e., within the 'reach' of the instruction request entry) that consume the produced value generated by the producer instruction are &#x201c;woken-up&#x201d; and subsequently indicated as ready to be issued.

Reach matrix scheduler circuit for scheduling instructions to be executed in a processor

In certain aspects of the disclosure, an apparatus comprises a first scheduling pool associated with a first minimum scheduling latency and a second scheduling pool associated with a second minimum scheduling latency, the second minimum scheduling latency greater than the first minimum scheduling latency. A common instruction picker is coupled to both the first scheduling pool and the second scheduling pool. The common instruction picker may be configured to select a first instruction from the first scheduling pool and a second instruction from the second scheduling pool, and then choose either the first instruction or second instruction for dispatch according to a picking policy.

Method, apparatus, and system for reducing live readiness calculations in reservation stations

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Combining load or store instructions

Operand pool instruction reservation clustering in a scheduler circuit in a processor is disclosed. The scheduler circuit includes a plurality of operand pool reservation circuits each having an assigned number of source operands for an instruction stored that must be ready before the instruction is issued. Instructions having the same number of source operands that are not yet ready for its issuance can be stored in an operand pool reservation circuit having the same assigned number of source operands. In this manner, the number of reservation entries and associated comparator circuits in the clustered scheduler circuit is distributed among the plurality of operand pool reservation circuits to avoid or reduce an increase in the number of scheduling path connections and complexity in each reservation circuit. This can avoid or reduce an increase in scheduling latency for a given number of reservation entries in the clustered scheduler circuit.

Operand pool instruction reservation clustering in a scheduler circuit in a processor

Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction. This reach-based explicit naming architecture does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is not limited to explicit naming of consumer instructions only within the same instruction block of the producer instruction.

Reach-based explicit dataflow processors, and related computer-readable media and methods

Performing flush recovery using parallel walks of sliced reorder buffers (SROBs) is disclosed herein. In one exemplary embodiment, a register mapping circuit provides a rename mapping table (RMT) comprising RMT entries representing logical register number (LRN) to physical register number (PRN) mappings. The register mapping circuit also provides an SROB comprising multiple SROB slices that each corresponds to a respective LRN. Each SROB slice tracks uncommitted instructions that write to the LRN corresponding to that SROB slice, and maintains those instructions in program order with respect to each other. Upon detecting an uncommitted instruction writing to an LRN, the register mapping circuit allocates an SROB slice entry in the SROB slice corresponding to the LRN. When an pipeline flush from a target instruction occurs, the register mapping circuit restores RMT entries of the RMT to their prior mapping states based on parallel walks of the SROB slices of the SROB.

Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)

A register mapping circuit for recovering a register mapping state associated with a flushed instruction by traversing ROB entries from a snapshot of another register mapping state. The register mapping circuit includes a ROB control circuit, a snapshot circuit, and a register rename recovery circuit (RRRC). The ROB control circuit allocates ROB entries to instructions entering a processor pipeline, including a target ROB entry allocated to a target instruction and other ROB entries allocated to other instructions. The snapshot circuit captures snapshots of logical register-to-physical register mapping states in the rename map table in association with a subset of instructions that could be flushed. If the target instruction is flushed, the RRRC restores the rename map table register mapping state corresponding to the target instruction based on a snapshot in a ROB entry allocated to another instruction, and traverses register mapping updates in the intervening ROB entries.

Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor

A processor element in a processor-based system is configured to fetch one or more instructions associated with a program binary, where the one or more instructions include an instruction having an immediate operand. The processor element is configured to determine if the immediate operand is a reference to a wide immediate operand. In response to determining that the immediate operand is a reference to a wide immediate operand, the processor element is configured to retrieve the wide immediate operand from a common intermediate lookup table (CILT) in the program binary, where the immediate operand indexes the wide immediate operand in the CILT. The processor element is then configured to process the instruction having the immediate operand such that the immediate operand is replaced with the wide immediate operand from the CILT.

Systems and methods for processing instructions having wide immediate operands

Latency-based instruction reservation clustering in a scheduler circuit in a processor is disclosed. The scheduler circuit includes a plurality of latency-based reservation circuits each having an assigned producer instruction cycle latency. Producer instructions with the same cycle latency can be clustered in the same latency-based reservation circuit. Thus, the number of reservation entries is distributed among the plurality of latency-based reservation circuits to avoid or reduce an increase in the number of scheduling path connections and complexity in each reservation circuit to avoid or reduce an increase in scheduling latency. The scheduling path connections are reduced for a given number of reservation entries over a non-clustered pick circuit, because signals (e.g., wake-up signals, pick-up signals) used for scheduling instructions in each latency-based reservation circuit do not have to have the same clock cycle latency so as to not impact performance.

Latency-based instruction reservation station clustering in a scheduler circuit in a processor

Operand-based reach explicit dataflow processors, and related methods and computer-readable media are disclosed. The operand-based reach explicit dataflow processors support execution of a producer instruction that explicitly names a target consumer operand of a consumer instruction in a consumer operand encoding namespace of the producer instruction. The produced value from execution of the producer instruction is provided or otherwise made available as an input to the named target consumer operand of the consumer instruction as a result of processing the producer instruction. The target consumer operand is encoded in the producer instruction as an operand target distance relative to the producer instruction. Instructions in an instruction stream between the producer instruction and the targeted consumer instruction that have no operands do not consume an operand reach namespace in the producer instructions. This provides for a deeper explicit consumer naming reach for a given bit size of the operand reach namespace.

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices is disclosed. In one exemplary embodiment, a processor-based device provides a move-immediate logic circuit that detects a move-immediate instruction comprising an immediate value and a destination register. For frequently encountered immediate values, the move-immediate logic circuit allocates a physical register from an immediate physical register file (IPRF), and writes an IPRF tag corresponding to the allocated IPRF register into a most-recent mapping table (MRT) entry for the destination register. Subsequent move-immediate instructions embedding the same immediate value, as well as other dependent instructions, may then obtain the immediate value from the IPRF register by accessing the MRT entry. Additionally, the PE provides a frequent immediate table (FIT) for tracking occurrences of immediate values, and allocates IPRF registers for a given immediate value only when a count of occurrences of that immediate value exceeds a FIT threshold.

Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices

Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor. Instructions may execute out of order in a processor. Information about the logical register-to-physical register mapping resulting from each instruction is stored in entries in program order in the ROB. When the pipeline is interrupted by an instruction that fails to execute, changing program flow, all instructions following the interrupting instruction may be flushed from the processor pipeline. It is important to return the state of the RMT to the state that existed when the interrupting instruction entered the pipeline. To recover the RMT state in response to an interrupting instruction, register mapping information in the ROB entries is traversed to either undo the younger instructions that entered the pipeline after the interrupting instruction or replay the older instructions that entered the pipeline before the interrupting instruction.

Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor

Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture is provided. In this regard, an OOP-based device provides a register management circuit that is configured to employ a combination of the checkpoint approach and the virtual register approach. The register management circuit includes a most recent table (MRT) for tracking mappings of logical register numbers (LRNs) to physical register numbers (PRNs), a physical register file (PRF) storing information for physical registers, a virtual register file (VRF) storing data for virtual registers, and a checkpoint queue for tracking active checkpoints (each of which is a snapshot of the MRT at a given time). The register management circuit applies checkpoint selection criteria for balancing the number of checkpoints, and implements late physical register allocation using virtual registers to provide an effectively larger physical register file and checkpoint-based early release of physical registers.

Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture

Growing community of inventors

Raleigh, NC, United States of America

Rodney Wayne Smith