Siliconsystems, Inc.

Rodney T Masumoto

Shunsaku Ueda

Jenn-Gang Chern

Kirby Lam

The present invention provides a method and an apparatus for controlling and measuring the phase window of a data separator that is suitable for implementation in an automatic test equipment (ATE) system. The test circuit comprising cross-coupled flip-flops uses the pump up (PU) and pump down (PD) signals produced by a phase detector of a phase-locked loop (PLL) to digitally monitor the phase window. The PLL captures a fixed frequency data pattern provided to the data separator and tracks its frequency. The clock inputs of the cross-coupled flip-flops are driven by the pump up and pump down signals output by the phase detector. Once the PLL has captured the fixed frequency data pattern and settled, a single data bit is shifted from its initial position in the center of the phase window. The single data bit is shifted so that its phase leads or lags its initial position. When the single data bit is shifted in the data pattern, the phase detector correspondingly sets PU high, PD high, or both PU and PD high. By shifting the data bit so that its phase is first leading and then lagging, or vice versa, until the flip-flops change state, the edges of the phase window are determined. Due to the digital nature of this test circuit, the phase window of a data separator can be accurately measured by an ATE system.

Phase window test circuit

The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 .mu.s). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted. By utilizing a start-up sequence, the center frequency of the VCO is already settled when changing frequencies, the divide-by-M and divide-by-N counters are matched, the VCO starts in phase with the reference frequency of the reference signal, and the voltage of the loop filter is prevented from railing. By using dual buffered registers for each counter, loading of the divide-by-M and divide-by-N counters is accomplished without shutting down the VCO. A timer provides a 1.6 .mu.s delay to allow the DAC to settle. Digital logic is used to synchronize signals. Delay compensation circuitry is used to implement delay cancellation for zero phase restart.

Time based data separator zone change sequence

A one-shot control mechanism for ensuring close tracking of one-shot period to VCO period. The one-shot control mechanism provides immunity to data jitter and other spurious phenomena as well as stable and accurate tracking of one-shot period even when the VCO frequency varies from the center frequency of the VCO. The present invention includes a data capture PLL circuit and a frequency reference PLL circuit. The frequency reference PLL circuit provides a control signal to one or more one-shots to control their output pulse duration. Since the frequency reference PLL circuit operates at the expected frequency of data input, a relatively constant relationship may be maintained between the output pulse duration of the one-shots and the period of the VCO output.

One-shot control circuit for tracking a voltage-controlled oscillator

A zero-phase restart circuit that provides a new circuit element in the path of the incoming data signal in order to delay the data signal by an amount equal to the delay caused by the restart circuitry. This ensures that the phase difference between the two signals will be zero at restart and thus effectively cancels out the residual error seen with the prior art. This technique remains effective well into higher data rates. The advantages of the present invention allows the circuit to operate near its limit without suffering large transients on the VCO control voltage and the VCO frequency. The overall system will not be limited by the transient response on the VCO control voltage nor the VCO frequency. It allows for higher operating speeds of data. Further, the new method will allow the system to better tolerate the jitter of the incoming data such that the restrictions on the jitter performance of the incoming data can be reduced substantially, i.e., allow more jitter to exist on the data.

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Tustin, CA, United States of America

Rodney T Masumoto