Applied Materials, Inc.

Rodney Shunleong Lim

Jung Bae Kim

Soo Young Choi

Yi Cui

Jiarui Wang

Dong-Kil Yim

Dong Kil Yim

Tae Kyung Won

Xuena Zhang

Won Ho Sung

Yun-chu Tsai

Hao-Chien Hsu

Yang Ho Bae

Dejiu Fan

A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

Transistor devices with multi-layer interlayer dielectric structures

Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack is provided and includes a silicon oxide layer disposed on a workpiece, a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer. The hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

Nitrogen-rich silicon nitride films for thin film transistors

Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, methods for depositing silicon nitride materials are provided and include heating a workpiece to a temperature of about 200&#xb0; C. to about 250&#xb0; C., exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition process, and depositing a nitrogen-rich silicon nitride layer on the workpiece. The deposition gas contains a silicon precursor, a nitrogen precursor, and a carrier gas. A molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas within the deposition gas is about 1:a range from about 4 to about 8:a range from about 20 to about 80, respectively.

Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack contains a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at % to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at %, and a hydrogen concentration of about 10 at % to about 35 at %. In one or more examples, the passivation film stack contains the silicon oxide layer, the nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride, such as nitrogen-rich silicon nitride and/or hydrogen-rich silicon nitride.

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

Surface treatment process performed on devices for TFT applications

Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide layer and treating the metal oxide layer with a fluorine containing gas or plasma. The fluorine treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

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Daly City, CA, United States of America

Rodney Shunleong Lim