The Boeing Company

Rodney Kevin Bonebright

Mark William Steeds

Jay W Clement

Frank R Brogden

Robert G Ford

Jacob C Killens

Alfio Zanchi

Rodney Alan Hughes

Brian Kenneth Kormanyos

John H Nitardy

Thomas H Friddell

Harold J Redd

Michael H Florian

Eric M Kawalsky

Gary Wilsey

Paul E Jeroma

David R Hogue

Frank R Brodgen

A phased array antenna system includes a plurality of radio frequency (RF) tile sub-arrays. Each RF tile sub-array includes a multiplicity of RF elements, a tile control integrated circuit, a multiplicity of RF integrated circuits and a configuration storage device. The configuration storage device stores data including calibration and configuration information that is unique to the RF tile sub-array and the tile control integrated circuit. The multiplicity of RF integrated circuits, the multiplicity of RF elements, and the configuration storage device are disposed on a single associated RF tile sub-array. The system also includes an antenna controller configured to process data for steering or tracking one or more RF beams by the multiplicity of RF elements. The calibration and configuration information that is unique to the RF tile sub-array is downloaded from the configuration storage device through the tile control integrated circuit to an RF element compensation table.

Phased array antenna system including a modular control and monitoring architecture

A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADCs, an open-loop clocking circuit, and a time-multiplexing circuit. The plurality of ADCs receive an analog input signal. Each ADC is configured to sample the analog input signal upon receipt of a respective clock signal. The open-loop clocking circuit receives a main clock signal having a reference frequency, and then divides the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal starting from the main clock signal. The open-loop clocking circuit then distributes the plurality of respective clock signals to the plurality of ADCs. The time-multiplexing circuit is coupled to the plurality of ADCs and is configured to combine respective digital output signals from the plurality of ADCs into a time series.

Clocking circuit and method for time-interleaved analog-to-digital converters

Systems and methods are provided for regulating heat for a Phased Array Antenna (PAA). The system includes a PAA, which includes array elements to handle Radio Frequency (RF) signals. The PAA also includes a circuit. The circuit includes an amplifier that operates on a current to amplify signals for the PAA, and a sensor that measures temperature at the MMIC. The PAA also includes an array controller that adjusts the current for the amplifier based on a temperature measured by the sensor.

Heat regulation for components of phased array antennas

Systems and methods according to one or more embodiments are provided for a true time delay function. The true time delay function may be implemented, for example, as a selectable signal delay circuit for broad bandwidth time control of phased array antenna element signals. In one example, a system comprises a selectable signal delay circuit including a plurality of delay lines, an input port, and an output port, wherein the delay lines are disposed between the input port and the output port. A plurality of amplifiers are coupled to corresponding ones of the plurality of delay lines and coupled between the input port and the output port. A plurality of switches are configured to selectively couple the plurality of delay lines and corresponding amplifiers to provide a selectable delay and amplification between the input port and the output port. Additional systems and methods are also provided.

Integrated true time delay for broad bandwidth time control systems and methods

An antenna array includes a plurality of power amplifiers, each having a signal input, a signal output coupled to a cell of the antenna array, and a power input. The antenna array includes a plurality of power supplies, each power supply individually and separately coupled to a corresponding one of the plurality of power amplifiers at a respective power input. The antenna array further includes single a pre-distortion linearizer with a linearizer input that receives a signal and a linearizer output that is coupled to each signal input of each of the plurality of power amplifiers. Each power amplifier is operated in gain compression by setting its operating voltage according to a power output of the power amplifier.

Simultaneous linearization of multiple power amplifiers with independent power

Systems and methods according to one or more embodiments are provided for a distributed gain function. The distributed gain function may be implemented, for example, as a second amplification stage to maintain amplification in an RF distribution network of a compact high gain phased array antenna system. In one example, a system comprises a plurality of element circuits, each coupled to one or more antenna elements. Each element circuit comprises a first amplification stage. A distribution network configured to couple the plurality of element circuits. A distributed gain circuit coupled to the plurality of element circuits and the distribution network, wherein the distributed gain circuit comprises a second amplification stage. The antenna elements and the distribution network are integrated in a substantially planar circuit board and the plurality of element circuits are coupled to the circuit board. Additional systems and methods are also provided.

Gain distribution in compact high gain phased array antenna systems and methods

Systems and methods according to one or more embodiments are provided for stacked active RF circuits implemented as amplification stages in high gain phased array antenna systems. Stacked active RF circuits may be implemented, for example, as an amplification stage of an element electronic circuit. Stacked active RF circuits may be implemented, for example, as a second amplification stage to maintain amplification in a high gain phased array antenna system. In one example, a system comprises a substrate comprising a plurality of substrate layers and one or more input ports and output ports. A plurality of amplification stages comprising a plurality of amplifiers, attenuators, and phase shifters are integrated within the plurality of substrate layers, the amplification stage coupled between the input and output ports. One or more monitor circuits are coupled to the plurality of amplification stages. Additional systems and methods are also provided.

Stacked active RF circuits including in-situ bias monitoring systems and methods

A transceiver (14) for recovering two different types of manchester coded, optical data signals from a photodiode is disclosed. The transceiver (14) includes a preamplifier (28) that receives and differentially amplifies the optical signal to reject power supply noise. The output of the preamplifier (28) is applied to an AC coupler (30) that extracts DC signal components using a switching circuit to produce a purely differential signal. A post amplifier/quantizer (34) receives the purely differential signal from the AC coupler (30) and generates a quantized signal therefrom. The quantized signal is applied to a data filter, clock recovery and control logic system 36 (36) that recovers a clock signal from the data signal that is synchronized by every data edge of the quantized signal.

Dual rate, burst mode, radiation hardened, optical transceiver

A bus leveling system for automatically monitoring and maintaining the amplitude of a radio frequency (RF) signal carded on a bus. A two-stage variable gain amplifier (64) is connected in series with the bus. Each stage of the variable gain amplifier is constructed with a PIN diode (84, 86) in a feedback path of the stage. The amplification of the variable gain amplifier is varied by the injection of current into the feedback path to adjust the resistance of the PIN diodes. A control circuit having an RE detector (78) is provided to monitor and adjust the gain generated by the variable gain amplifier. Preferably, the control circuit and the variable gain amplifier are incorporated into an Application Specific Integrated Circuit (ASIC) (62). The RF detector is constructed of two Gilbert multipliers (202, 204) to minimize errors caused by operating condition changes, including variations in power supply voltage, temperature, or process.

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Bellevue, WA, United States of America

Rodney Kevin Bonebright