Texas Instruments Corporation

Analog Devices,inc.

Rodney Dean Miller

James D Huffman

Ernest T Stroud

James M Florence

Barry L Stakely

Tyre Paul Lanier

Mark L Burton

George F Diniz

Jinhjiang Yin

Charles O'Roark

Jingang Yi

Ted Hecht, Jr

Henry C Chu

Robert J Gove

Donald B Doherty

Duane E Carter

Rabah Mezenner

Richard O Gale, Jr

Ralph David Moore, Jr

Robert E Meier

Richard O Gale

Brian L Ray

Harlan Paul Cleveland

Eric A Schmidt

Harian Paul Cleveland

Steven L Backer

A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.

Adaptable phase lock loop transfer function for digital video interface

Activation systems and methods initiate High-Definition Multimedia Interface (HDMI) communication between an HDMI source and an HDMI sink through an HDMI receptacle of the source. These systems and methods are especially suited for use with mobile sources that generally operate from a battery that cannot provide the +5V signal which the HDMI protocol requires sources to place on the +5V pin of their HDMI receptacles. These systems and methods automatically detect the insertion of an HDMI cable into the source's HDMI receptacle and subsequently generate and apply the required +5V signal to the +5V pin of the source's HDMI receptacle to initiate HDMI communication. Because they are directed to use in mobile sources, the embodiments are configured to minimize current drain.

Activation systems and methods to initiate HDMI communication with mobile sources

A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Self-test circuit for high-definition multimedia interface integrated circuits

A system and method transmits graphic data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

System and method of data transmission in tension members of a fiber optical system

A system and method transmits data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

System and method for synchronous clock re-generation from a non-synchronous interface

Phase-locked loop structures are provided that facilitate enhanced stability of loop-generated signals. They include an oscillator network, a feedback loop and a controller. The oscillator network generates a loop output signal with a frequency that varies in response to a control voltage and to a frequency-determining parameter, the feedback loop generates the control voltage in response to the loop output signal and a reference signal and the controller increments the frequency-determining parameter to maintain the control voltage within a predetermined control-voltage range. These structures enhance signal stability by facilitating the use of low-gain oscillator structures and they simplify and shorten loop operations because the structures operate in a closed-loop condition at all times.

Phase-locked loop structures with enhanced signal stability

An auxiliary line driver (,) able to sense data driven on a signal path (,) by a primary line driver (,), and then drive the data on the signal path (,). The auxiliary driver (,) allows a small primary line driver (,) to drive a large load, or a large number of loads (,) without consuming a large area in the region where the primary line driver (,) is fabricated. The auxiliary line driver is particularly useful for driving the memory array of a micromirror device, especially during a block clear operation in which a large number of memory cells (,) are written to simultaneously. When the auxiliary line driver (,) receives an enable signal (,), the auxiliary line driver drives the last input provided to the input of the auxiliary line driver (,).

Feedback driver for memory array bitline

An improved memory cell (,) for use in applications, such as micromirror arrays, in which little space is available and a slow read-back cycle is tolerated. The memory (,) comprises a first input/output node (,) connected to the input of a first inverter and to the output of a second inverter. The first inverter is comprised of two transistors (,) and drives a signal to a second input/output node (,). The input of the second inverter is connected to the second input/output node (,). When used to drive a typical micromirror cell, the address electrode of the micromirror cell are electrically connected to the first input/output node (,) and the second input/output node (,).

Five transistor SRAM cell for small micromirror elements

A spatial light modulator (70) comprised of an array of micromirrors (72) each having support post (74). The support post (74) defines support post edges (76) in the upper surface of the mirrors (72). These support post edges (76) are all oriented at 45 degree angles with respect to an incident beam of light from a light source (80) to minimize diffraction of light from the edges (76) into the darkfield optics when the mirrors are oriented in the off-state. The present invention achieves an increased contrast ratio of about 20% over conventional designs.

Spatial light modulator having improved contrast ratio

A micromirror array fabricated on a semiconductor substrate 708. The micromirrors in the micromirror array logically divided into an interior active region 704 which selectively modulates light striking the mirrors in the interior active region 704, and an exterior border region 702 for producing a dark border around the image produced by the interior active region 704. A gap between each mirror allows adjacent mirrors to rotate. The gap 712 between mirrors in the interior active region 704 of the array is larger than the gap 710 between at least some of the mirrors in the exterior border region 702. The smaller gap 710 in the exterior region 702 is enabled by restricting mirrors in the exterior region 702 to a single direction of rotation.

Reduced micromirror mirror gaps for improved contrast ratio

A DMD spatial light modulator (20) having an improved reset waveform (80) that improves the electrostatic control over the DMD mirrors (30) during switching states (T3). An intermediate bias level is provided to the yoke (32) and mirror (30) during the mirror reset cycle (T3) which is sufficient to maintain a voltage differential between the mirror/yoke and the address electrodes (26,28,50,52) to dynamically park the mirror during a same-state transition, but which voltage differential is insufficient to overcome the hinge restoration forces during an opposite-state transition such that the mirror releases toward the neutral position and can be captured in the other state upon reapplication of the bias voltage. The transition bias level is maintained for a sufficient time period (T3) to allow the mirror/yoke to release from the landing pads (82) a sufficient distance toward the neutral position. The operating reliability of the device is improved by preventing incident light during same-state mirror transitions from escaping into the display aperture, without impeding the crossover of the mirror during opposite-state mirror transitions. Greater mirror-to-mirror variations can be tolerated without falling outside the mirror arrays acceptable timing operating parameters.

Multiple bias level reset waveform for enhanced DMD control

A method of providing control signals for resetting mirror elements (10,20) of a digital micro-mirror device (DMD) having reset groups (FIG. 4), or for resetting moveable elements of other micro-mechanical devices that operate with similar principles. A bias voltage is applied to the mirrors and their landing sites, and an address voltage is applied under the mirrors. (FIG. 3). The address voltage is held at an intermediate level except during a reset period. During this reset period, the address voltage is increased. Also, during reset, the bias applied to mirrors to be reset is pulsed and offset, and the bias applied to mirrors not to be reset is increased. (FIGS. 5 and 6).

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Kernersville, NC, United States of America

Rodney Dean Miller