Ampex Corporation

Rodney D Stock

Lawrence J Evans

Junaid Sheikh

Thomas K Porter

Kenneth E Turkowski

A YIQ computer graphics system includes a data processing system having a data tablet for receiving inputs from an artist and a video processing system connected to the data processing system. The video processing system includes a two component expandable frame store with the first component storing video intensity information for each pixel of a visual image and with the second component storing two video color components each for one-half of the visual image. The video processing system further includes a memory controller coupled to receive pixel address information identifying pixel locations within a row and column matrix of pixel locations containing the visual image and addressing specific locations within the frame store in response thereto, an interface circuit coupled to transfer video data between the frame store and the data processing system at pixel locations within a matrix of locations defined by the data processing system, and a video output processor coupled to provide matrix address locations to the frame store and receive in return video data from the frame store to generate a color video output signal in raster scan order. The video processing system may also include an input scanner coupled to write into the frame store video information on a continuous frame-by-frame basis to permit the video output processor to output a video signal which indicates a continuously changing video image on a frame-by-frame real time basis.

YIQ Computer graphics system

VIQ Computer graphics system

A high frequency, high resolution programmable timing signal generator provides periodic timing signals during a time period which is long with respect to the time resolution of the generator. The timing signal generator which is particularly applicable for generation of the composite sync signal (and numerous related signals) for a video television signal, includes a small, high speed random access memory wherein each word corresponds to a timing state and each output bit provides a sync video related signal. Other memory bit outputs operate in conjunction with control and timing circuitry to sequentially address the memory while permitting the memory to remain in a given state for predetermined time durations and to cyclically repeat selected state sequences. Memory word compaction is thus facilitated to permit the use of small, fast memories to provide precision implementation of complex timing functions over relatively long frame period intervals with wide flexibility.

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Palo Alto, CA, United States of America

Rodney D Stock