Motorola Corporation

Rodney C Tesch

James Douglas Dworkin

Michael J Torla

Jerry D Moench

John Michael Buss

Robert I Foster

Scott Alexander Vanstone

William J Donoghue

A co-processor ( ) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier ( ) receives sixteen bit data values stored in an A/B RAM ( ) and generates a partial product. The generated partial product is summed in an adder ( ) with a previous partial product stored in a product RAM ( ). A modulo reducer ( ) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM ( ) stores the data value N that is added in a modulo reducer ( ) to the summed value. The co-processor ( ) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method for fast modular multiplication

A co-processor (,) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (,) receives sixteen bit data values stored in an A/B RAM (,) and generates a partial product. The generated partial product is summed in a summer (,) with a previous partial product stored in a product RAM (,). A modulo reducer (,) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (,) stores the data value N that is added in a modulo reducer (,) to the summed value. The co-processor (,) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method of modulo multiplication

A Galois Field arithmetic logic unit (GF ALU) circuit (200) that generates a GF product of size M includes a first and a second input field element register (205, 210), a result field element register (215), a plurality, I, of subfield sets of logic gates (255, 260, 265), a plurality, S, of extension sets of logic gates (270, 275), and 3M switches (135). M is equal to S multiplied by I. A Galois Field of size M, S, and I each has an optimal normal basis. The first and second input field element registers (205, 210) are alternately coupled to the result field element register (215) by the I subfield sets of logic gates (255, 260, 265) in a first configuration and by the S extension sets of logic gates (270, 275) in a second configuration. The 3M switches (135) alternate the first and second configurations.

Galois field arithmetic logic unit circuit

A pull-up circuit for a memory provides an additional natural transistor between a power supply and diode-connected transistors which reduces the voltage on bit sense lines sufficiently to allow selected column select transistors to turn on prior to a memory cell being enabled. Additional control circuitry further reduces the voltage to the diode-connected transistors when no memory cells have been selected to be enabled to compensate for the reduction in voltage drop across the natural transistor when no current is flowing through it.

Pull-up circuit for a memory

A substrate bias regulator useful for controlling a variable output oscillator and/or a substrate bias voltage generator is provided to control the substrate voltage on a semiconductor chip. A series of field effect transistors are arranged in a manner to sense the substrate voltage and to provide an output to regulate the substrate voltage. One of the series field effect transistors has its gate electrode connected to reference potential ground which tends to make the regulator independent of transistor thresholds.

Substrate bias regulator

There is provided a circuit capable of speeding up a signal that has a positive slope, dv/dt&gt;0. The circuit detects or senses the slope, amplifies the slope and feeds back a signal to enforce the pull up of the positive going signal. The circuit is also capable of handling complementary signals and when the positive going signal is being pulled up its complement is pulled down. The positive going signal is capacitively coupled into the circuit.

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Phoenix, AZ, United States of America

Rodney C Tesch