Lam Research Corporation

Cabot Microelectronics Corporation

Cabot Corporation

Rodney C Kistler

Yehiel Gotkis

Aleksander Owczarz

Vlasta Brusic Kaufman

David J Hemker

Nicolas J Bright

Shumin Wang

David Wei

Damon Vincent Williams

Bruno Morel

Vladimir Katz

Brian L Mueller

Christopher C Streinz

Dave Hemker

Te Hua Lin

Debra L Scherber

Leonid Romm

Charles Freund

Slumin Wang

Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

Method for making semiconductor structures implementing sacrificial material

A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.

Semiconductor structure implementing sacrificial material and methods for making and implementing the same

A chemical mechanical polishing slurry comprising an oxidizing agent, a complexing agent, an abrasive, and an optional surfactant, as well as a method for using the chemical mechanical polishing slurry to remove copper alloy, titanium, titanium nitride, tantalum and tantalum nitride containing layers from a substrate. The slurry does not include a separate film-forming agent.

Chemical mechanical polishing slurry useful for copper substrates

A semiconductor processing system is provided. The semiconductor processing system includes a first sensor configured to isolate and measure a film thickness signal portion for a wafer having a film disposed over a substrate. A second sensor is configured to detect a film thickness dependent signal in situ during processing, i.e. under real process conditions and in real time. A controller configured to receive a signal from the first sensor and a signal from the second sensor. The controller is capable of determining a calibration coefficient from data represented by the signal from the first sensor. The controller is capable of applying the calibration coefficient to the data associated with the second sensor, wherein the calibration coefficient substantially eliminates inaccuracies introduced to the film thickness dependent signal from the substrate. A method for calibrating an eddy current sensor is also provided.

Method and apparatus for real time metal film thickness measurement

A method for minimizing measuring spot size and noise during film thickness measurement is provided. The method initiates with locating a first eddy current sensor directed toward a first surface associated with a conductive film. The method includes locating a second eddy current sensor directed toward a second surface associated with the conductive film. The first and second eddy current sensors may share a common axis or be offset from each other. The method further includes alternating power supplied to the first eddy current sensor and the second eddy current sensor, such that the first eddy current sensor and the second eddy current sensor are powered one at a time. In one aspect of the invention, a delay time is incorporated between switching power between the first eddy current sensor and the second eddy current sensor. The method also includes calculating the film thickness measurement based on a combination of signals from the first eddy current sensor and the second eddy current sensor. An apparatus and a system are also provided.

Method and apparatus of arrayed, clustered or coupled eddy current sensor configuration for measuring conductive film properties

A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A cluster of sensors external to the CMP tool is included. The cluster of sensors is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The cluster of sensors provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.

Integration of sensor based metrology into semiconductor processing tools

A method and an apparatus for enhancement of the for measuring resistance-based features of a substrate is provided. The apparatus includes a sensor configured to detect a signal produced by a eddy current generated electromagnetic field. The magnetic field enhancing source is positioned to the alternative side of the object under measurement relative to the sensor to enable the sensitivity enhancing action. The sensitivity enhancing source increases the intensity of the eddy current generated in the object under measurement, and as a result the sensitivity of the sensor. A system enabled to determine a thickness of a layer and a method for determining a resistance-based feature characteristic are also provided.

Enhancement of eddy current based measurement capabilities

A method for converting a slope based detection task to a threshold based detection task is provided. The method initiates with defining an approximation equation for a set of points corresponding to values of a process being monitored. Then, an expected value at a current point of the process being monitored is predicted. Next, a difference between a measured value at the current point of the process being monitored and the corresponding expected value is calculated. Then, the difference is monitored for successive points to detect a deviation value between the measured value and the expected value. Next, a transition point for the process being monitored is identified based on the detection of the deviation value. A processing system configured to provide real time data for a slope based transition and a computer readable media are also provided.

Method and apparatus for slope to threshold conversion for process state monitoring and endpoint detection

A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

Semiconductor structure implementing low-K dielectric materials and supporting stubs

A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A sensor array external to the CMP tool is included. The sensor array is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The sensor array provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.

Method and apparatus of arrayed sensors for metrological control

In chemical mechanical polishing apparatus, a wafer carrier plate is provided with a cavity for reception of a sensor positioned very close to a wafer to be polished. Energy resulting from contact between a polishing pad and an exposed surface of the wafer is transmitted only a very short distance to the sensor and is sensed by the sensor, providing data as to the nature of properties of the exposed surface of the wafer, and of transitions of those properties. Correlation methods provide graphs relating sensed energy to the surface properties, and to the transitions. The correlation graphs provide process status data for process control.

Apparatus and methods for detecting transitions of wafer surface properties in chemical mechanical polishing for process status and control

A system and method of measuring a metallic layer on a substrate within a multi-step substrate process includes modifying a metallic layer on the substrate such as forming a metallic layer or removing at least a portion of the metallic layer. At least one sensor is positioned a predetermined distance from the surface of the substrate. The surface of the substrate is mapped to determine a uniformity of the metallic layer on the surface of the substrate.

System and method for metal residue detection and mapping within a multi-step sequence

In chemical mechanical polishing, a wafer carrier plate is provided with a cavity for reception of a sensor positioned very close to a wafer to be polished. Energy resulting from contact between a polishing pad and an exposed surface of the wafer is transmitted only a very short distance to the sensor and is sensed by the sensor, providing data as to the nature of properties of the exposed surface of the wafer, and of transitions of those properties. Correlation methods provide graphs relating sensed energy to the surface properties, and to the transitions. The correlation graphs provide process status data for process control.

Methods for detecting transitions of wafer surface properties in chemical mechanical polishing for process status and control

A method for detecting a thickness of a layer of a wafer to be processed is provided. The method includes defining a plurality of sensors configured to create a set of complementary sensors proximate the wafer. Further included in the method is distributing the plurality of sensors along a particular radius of the wafer such that each sensor of the plurality of sensors is out of phase with an adjacent sensor by a same angle. The method also includes measuring signals generated by the plurality of sensors. Further included is averaging the signals generated by the plurality of sensors so as to generate a combination signal. The averaging is configured to remove noise from the combination signal such that the combination signal is capable of being correlated to identify the thickness of the layer.

Complementary sensors metrological process and method and apparatus for implementing the same

An ironing assembly for use in chemical mechanical planarization (CMP) is provided. The ironing assembly is designed for use over a linear polishing pad which has a plurality of asperities and applied slurry. The ironing assembly includes an ironing disk having a contact surface. The ironing disk is oriented over the linear polishing pad such that the contact surface of the ironing disk can be applied over the surface of the linear polishing pad to at least partially flatten the plurality of asperities before planarizing a semiconductor wafer surface over the linear polishing pad.

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St. Charles, IL, United States of America

Rodney C Kistler