National Semiconductor Corporation

The Boeing Company

Crane Electronics, Inc.

Rodney Alan Hughes

Jay Allen Kuehny

Reid Adriance

Bertrand Nkei

Michael S Foster

Rodney Kevin Bonebright

John H Nitardy

Jay W Clement

James C Braatz

Barry F Waltman

Tuan A Dao

An oscillator formed from low cost discrete semiconductors and passive devices creates a linear periodic ramp of constant frequency with ramp slope based on an external voltage signal. Parameters are stable over a wide range of temperatures and variations of transistor parameters that normally degrade in extreme environments. The oscillator period can be phase and frequency synchronized to an external clock source over a wide range of frequencies. The oscillator ramp generator phase can be synchronized on a cycle by cycle basis for incorporation in power converters employing spread spectral EMI reduction techniques, multi-converter systems employing clock interleaving for distribution bus filter optimization, and resonant mode converters employing zero voltage switching techniques. Oscillator ramp rate is independent of frequency and can be synchronized to DC (inhibit) for use in ultra low power burst mode power conversion.

Oscillator apparatus and method with wide adjustable frequency range

Control circuitry handles inrush current, and may provide under voltage and/or over voltage monitoring and handling, as well as remote enable handling. The circuitry may advantageously employ a sense capacitor in parallel with an input capacitor (e.g., bulk input filter capacitor), and a current mirror to produce a signal proportional to input current. A clamp circuit may control a series pass device to regulate current in response to the proportional signal, or to interrupt current flow in response to an under voltage or over voltage condition or receipt of a signal indicative of a disable state. An enable signal may be summed into a comparator that handles under voltage condition determination.

Input control apparatus and method with inrush current, under and over voltage handling

An auxiliary power supply or bias voltage supply employs a step up switch mode DC/DC power converter topology to supply regulated bias supply voltages, from very low input voltages (e.g., less than 2V). The supply will synchronize to dynamic loads making it particularly useful in circuits with periodic high peak current power demands, for example, gate drive circuits employed in regulated switched mode power converters. When unladed, the supply will efficiently adjust its cycle period to the minimum required to maintain the desired boosted output voltage. Additional transformer windings or a charge pump may be used to generate additional vias voltage sources.

Self synchronizing power converter apparatus and method suitable for auxiliary bias for dynamic load applications

An output stage of an amplifier circuit includes one or more output transistors that are selectively driven by a boosted drive circuit, where the boosted drive circuit is arranged such that the output range of the amplifier circuit is increased while maintaining reduced quiescent current. The drive signal to each output transistor is selectively increased only when demanded by the output load conditions. The threshold for boosting the drive signal can be adjusted for optimized performance. In one example, a class AB output stage includes a separate drive boost circuit for each output transistor. For this example, each drive boost circuit has a separate threshold for boosting each of the drive signals to the output transistors. The boosting can also be adjusted to optimize the differential input stage and current mirror maximum current requirement while maintaining minimum required bias currents.

Amplifier output stage with extended operating range and reduced quiescent current

A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.

Gain adjustment for programmable gain amplifiers

A transceiver providing Fiber Channel data transfer speeds may be implemented in a lower performance process technology as a single unit, thereby reducing cost. A serializer and deserializer each having multiple lower frequency clocks are provided to obtain the equivalent of a high speed clock capable of use in Fiber Channel systems. Lower speed parallel data is converted to higher speed serial data, and vice versa. A digital frequency counter along with a phase detection circuit provides synchronization. Comma detection is provided for data word alignment.

Fibre channel transceiver

A linear voltage-controlled capacitance circuit is provided that includes a plurality of differentially coupled metal-oxide-semiconductor (MOS) varactor pairs. Each MOS varactor pair is operable to receive a same tuning voltage and to receive a bias voltage unique to the MOS varactor pair. The capacitance circuit is operable to generate a positive tank node signal and a negative tank node signal based on the tuning voltage and the bias voltages.

Voltage-controlled capacitance linearization circuit

A programmable gain amplifier includes a first gain setting circuit and a second gain setting circuit that are both coupled to an output of an amplifier. A trim adjustment circuit is and arranged to complete feedback to the amplifier by digitally panning between the first gain setting and the second gain setting based on a trim setting. The trim setting can be provided by a look-up table that is indexed with gain settings. The first and the second gain setting circuits can each include an array of series coupled resistors, where a tap point from each array is selectively coupled to the trim adjustment circuit for adjusting the overall gain. The first and second gain setting circuits can be matched to one another, with the addition of a gain offset circuit that is configured to skew the nominal gain values between the first and second gain setting circuits.

Programmable gain trim circuit

A charge pump comprises a first current mirror that injects a first charging current onto a loop filter and a second charging current onto an integrator capacitor. The first and second charging currents are controlled by a first common control signal. The first charging current mirrors the second charging current. A second current mirror drains a first discharging current from the loop filter and a second discharging current from the integrator capacitor. The first and second discharging is currents are controlled by a second common control signal. The first discharging current mirrors the second discharging current. A sampling circuit couples the second charging and discharging currents to the integrator capacitor, which charges or discharges with a difference current between the second charging and discharging currents. A control circuit detects a voltage difference between the loop filter and integrator capacitor and adjusts the first common control signal to minimize the voltage difference.

Charge pump using dynamic charge balance compensation circuit and method of operation

A linear voltage controlled capacitance circuit is provided that includes a plurality of MOS varactor pairs. Each MOS varactor pair is operable to receive a first tuning voltage, a second tuning voltage, and a bias voltage unique to the MOS varactor pair. The capacitance circuit is operable to generate a positive tank node signal and a negative tank node signal based on the first and second tuning voltages and the bias voltages. A means to control voltage-to-capacitance gain is also provided to compensate for coarse tuning capacitance change.

Linear voltage controlled capacitance circuit

A system and method for providing synchronous clocking allows for precise control of the phase relationship of the clocking signals to thereby provide accurate duty cycles for proper system operation. A digital logic circuit, such as a D-type flip-flop, is provided with a phase signal and clock signal having a frequency relationship. The output of the digital logic circuit is a function of the phase signal and clock signal. The synchronous output may be provided to multiple locations within a system to allow for a synchronous local clock in each of the locations.

Generation of synchronized clocks to multiple locations in a system

A charge pump comprises a first current mirror that injects a first charging current onto a loop filter and a second charging current onto an integrator capacitor. The first and second charging currents are controlled by a first common control signal. The first charging current mirrors the second charging current. A second current mirror drains a first discharging current from the loop filter and a second discharging current from the integrator capacitor. The first and second discharging currents are controlled by a second common control signal. The first discharging current mirrors the second discharging current. A sampling circuit couples the second charging and discharging currents to the integrator capacitor, which charges or discharges with a difference current between the second charging and discharging currents. A control circuit detects a voltage difference between the loop filter and integrator capacitor and adjusts the first common control signal to minimize the voltage difference.

A charge pump for injecting a charging current onto a loop filter when a pump control signal is enabled. The charge pump comprises: i) MOS output transistors for injecting or removing the charge onto the loop filter; ii) pre-charge capacitors for storing pre-charge voltages at least equal to the desired gate-to-source voltages of the output transistors; and iii) switching circuitry for coupling the pre-charge capacitors to the gates of the output transistors when the Pump Up and/or Pump Down signals are enabled. The appropriate pre-charge voltage turns on the appropriate output transistor and the charging and/or discharging current is adjusted to a final level determined by the desired gate-to-source voltages and monitoring circuits.

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Tacoma, WA, United States of America

Rodney Alan Hughes