Fujitsu Corporation

Stmicroelectronics Gmbh

Rodney A Mattison

Aaron Wade Wilson

David E Norton, Jr

Russell B Josephson

A method, and a system for implementing such method, for use in a magnetic disk storage system for compensating for variation in spin speed of a data storage media from a nominal or design spin speed. The method includes providing the nominal spin speed for the data storage media in the particular magnetic disk storage system and then measuring the actual spin speed of the data storage media. In one preferred embodiment, the spin speed measurement is completed by measuring the time from one servo position field to the next sequential servo position field in a track on the data storage media. Next, the present spin speed variation is determined by comparing the measured spin speed with the nominal spin speed. A correction factor is calculated based on the spin speed error and applied to at least one data transfer parameter, such as channel reference frequency or read/write gate assertion timing, prior to a subsequent data transfer process (i.e., a read or a write operation). The spin speed compensation method may further include verifying that the measured spin speed is within a range of acceptable spin speeds. The range of acceptable spin speeds is determined based on maximum spin speed change rates of the magnetic disk storage system and the most recent measured spin speed. If the measured spin speed is outside this range, the data transfer operation, i.e., a write operation, is stopped to prevent damaging data previously stored on the data storage media.

Method and system for compensation for spin speed variation in a magnetic disk storage device

A variable delay circuit, known as a delayed read data single shot (DRDSS) circuit, adapted for use in a data read channel which reads signals recorded with different clock frequencies in different zones on a data storage device, wherein the read channel includes a variable oscillator whose reactive impedance is supplied with a charging current whose level corresponds to the clock frequency of the zone being read. A current duplicator produces an output current that is a substantially identical duplicate of the charging current to provide an output level as a function of that output current, this output level being compared to a ramp signal, whereby a delayed version of the signal read from the data storage device is produced when the ramp signal is substantially equal to the output level. The ramp signal is generated by a ramp generator having a reactive impedance that is substantially identical to the reactive impedance of the variable oscillator, and that is charged when a signal is read from the data storage device.

Window margining apparatus with delayed read data single shot (DRDSS)

Variable delay circuit including current mirror and ramp generator

A write precompensation circuit employs a frequency synthesizer for providing a variable timing signal linked to variable transfer rate in a track zone recording system of a disk drive. The synthesizer also provides an operating frequency current sense signal that is used to generate bit shift of data bits being recorded. A ramp voltage on a ramp capacitor and a logic signal from a bit shift decision circuit are determinative of the magnitude and direction of bit shift, early or late. The VCO and its capacitor are formed on the same IC chip as the ramp capacitor thereby minimizing mismatch due to tolerances inherent in production and operation of electrical components.

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Louisville, CO, United States of America

Rodney A Mattison