Nxp B.v.

Koninklijke Philips Corporation N.V.

U.S. Philips Corporation

Rodger Frank Schuttert

Johannes De Wilde

Franciscus Gerardus Maria De Jong

Gerrit Willem Den Besten

Jose De Jesus Pineda De Gyvez

Hendrik Johannes Bergveld

Tom Waayers

Geertjan Joordens

Franciscus G De Jong

Mathias N Muris

Amir Zjajo

Mathias N M Muris

Bernardus Martinus Johannes Kup

Franciscus G M De Jong

Willem Franciscus Slendebroek

Albertus Jan Paulus Maria Van Uden

A method of testing a data transmission and reception system comprises sending a test signal from a transmitter () of the system to a receiver () of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.

Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller

High Speed I/O interfaces such as DVI, S-ATA or PCI-Express require expensive test equipment. Loop-back tests are widely used as one alternative, but lack coverage of timing-related defects. A system and method for on-chip jitter injection using a variable delay with controllable amplitude and high accuracy is provided that improves the coverage of loop-back tests.

System and method for on-chip jitter injection

Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop () as a function of a logic level of an integrated circuit. A logic level crossing condition of the integrated circuit is indicated as a function of the reset condition of the flip flop. In one implementation, the flip-flop is reset when the logic level is different than an expected logic level. In another implementation, a pair of flip-flops () are implemented such that only one flip-flop is reset at a particular logic level; if the logic level crosses, both flip-flops are reset. The aforesaid condition of both flip-flops being reset is used to indicate the logic level crossing.

Circuit interconnect testing arrangement and approach therefor

An integrated circuit (IC) comprises a plurality of analog stages (-), each of the analog stages being conductively coupled to a power supply (-), and being conductively coupled to each other by a signal path (); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus () coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus () for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches () in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register () for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor () may be present in the power supply to facilitate structural testing of the analog stages in isolation.

Analog IC having test arrangement and test method for such an IC

A plurality of integrated circuits that are used in an electronic circuit have functional interconnections and dedicated test connections. The integrated circuits receive and transmit synchronization information, such as clock signals from one integrated circuit to another successively through the chain. This permits a high-test speed. Preferably the synchronization information is serialized with test data, test results and/or commands. Preferably, the bit rate between successive integrated circuits in the chain is programmable by means of commands transmitted through the chain. Thus, different bit rates may be at different locations along the chain to reduce the delay occurred by the synchronization signals along the chain.

Testing of electronic circuits

An integrated circuit device has boundary scan structure coupled between a test input and the test output. The test register structure is used to shift information from the test input to a test output. The test shift register structure contains a data shift part coupled to connections for a functional circuit under test. In parallel with the data shift part is an instruction shift structure. By means of test control signals it is controlled whether instruction information travels from the test input to the test output through the instruction shift part or through the data shift part. The instruction shift part controls operation of the device in a test mode. A sensor is provided for sensing a physical operating parameter of the device. The sensor has an output coupled to the shift register structure for feeding a sensing result to the test output from the instruction shift part.

Boundary scan circuit with integrated sensor for sensing physical operating parameters

An integrated circuit assembly contains a carrier and a semi-conductor integrated circuit chip . A current path on the carrier supplies power to power supply connection of the chip. A magnetic field sensor is provided on the carrier in a vicinity of the current path, for sensing a magnetic field generated by a current through the current path. The assembly contains test-accessible electronic interface to the magnetic field sensor, for testing presence of the current. Preferably the sensors are integrated on the carrier by depositing magneto resistive material and patterning the material so as to provide sensors in the vicinity of current paths. Also preferably, the carrier is an interposer with connecting wiring, which is packaged with one or more integrated circuit chips before mounting the interposer on a printed circuit board

Integrated circuit with power supply test interface

Power supply connections to an integrated circuit are tested. The power supply connections are connected to a power supply conductor in the integrated circuit. For the test, combinations of current drawing circuits are switched on near the point where the power supply connection under test is connected to the power supply conductor. The current drawing circuits draw a considerable current, so as to cause a detectable voltage drop over the power supply connection, if this connection is operational. Different subsets of the current drawing circuits are activated successively. To prevent that all of the current drawing circuits are switched on at the same time by error, activation of each subset is controlled by a signal indicative of completion of activation of the preceding subset. A respective signal line is provided for each subset, to provide the signal for the subset.

Test circuit and test method for protecting an IC against damage from activation of too many current drawing circuits at one time

Integrated circuit with a test interface for testing a conductive connection between a supply pad and a supply of a functional block in the integrated circuit. A current test circuit has test inputs coupled to a first and a second point along the conductive connection, for comparing a voltage across the test inputs with a threshold. The current test circuit contains a threshold shifting circuit for shifting the threshold to a shifted value dependent on a voltage across the test inputs when the threshold shifting circuit is active. Testing is executed in two steps, making the threshold shifting circuit active when a first voltage is applied across test inputs and comparing a second voltage at the test input with the shifted threshold. One of the first and second voltage is a voltage drop across the connection when the integrated circuit is set to draw current along a connection, the other one of the first and second voltage is a reference voltage. In an embodiment the integrated circuit has a shunt circuit to provoke current through the conductive connection under test in parallel with current through the functional block.

Integrated circuit with test interface

The invention relates to a method of testing interconnections in integrated circuit (IC) assemblies. Hereto, a test signal is applied to an IC pin (,) providing an input terminal to the interconnection. In known methods, such as the boundary-scan method, a response signal is measured on an output terminal of the interconnection, provided by a further IC pin. According to the invention, however, a response signal is evaluated which is generated on the same terminal (,) as to which the test signal is applied. This has the advantage that the method of the invention can be applied when only one end of the interconnect to be tested can be supplied with appropriate test hardware. The method is particularly suited for testing a capacitance (,) between an IC pin (,) and a supply line, e.g. a ground line.

Connection test method

A testable circuit comprises a signal path having a time-dependent response behavior (for example, a high-pass filter behavior). The signal path is tested for faults. To this end, the circuit is switched to a test mode in which the signal path is isolated from other signal paths. Subsequently, a test signal containing a signal transition is applied to the input of the signal path and it is tested whether the signal on the output of the signal path at any instant exceeds a threshold level during a predetermined time interval after the transition. The result is loaded into a register and read from the circuit.

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Eindhoven, Netherlands

Rodger Frank Schuttert