International Business Machines Corporation

Roderick Michael West

Edward Kelley Evans

Daniel Joseph Liguori

Elliot N Linzer

Peter Hans Westerink

Nicholas David Butler

Brian J Machesney

Roy Childs Flaker

Darwin P Rackley

Matthew Damian Bates

Todd Williams

Richard J Grupp

Kathryn E Rickard

Gregory J Schroer

David D Litten

Stephen B Barrett

Christopher J Melhuish

Peter Casavant

Hiroyuki Ando

Andrew Anthony Long

A graphics display subsystem providing internally timed time-varying properties of display attributes is provided. The graphics display subsystem comprises a display device for displaying consecutive image frames of pixels having a variable display property, and a circuit for transferring image frames to the display device. One or more pixels are selected when a display attribute associated with the one or more pixels is set in an attribute table. The circuit varies, during a selected time interval, the display property of the selected pixels being displayed on the display device. In preferred embodiments, the variable display property is either a stereo image display, an image brightness control, or an image-blending control.

Graphics display system and method for providing internally timed

A method and apparatus which produces a semitransparent cursor for a video display presenting simultaneous viewing access to both the cursor and the underlying image information. At the on-screen location of the cursor, the viewer is able to simultaneously view and distinguish between the cursor and the underlying graphical data. In one form, the method includes the steps of obtaining the red, green, and blue video pixel data for each pixel representing at least a portion of the cursor; halving the numerical value of each datum of red, green, and blue video pixel data; injecting a binary value into the most significant bit of each datum to obtain modified red, green, and blue video pixel data; and providing modified red, green, and blue video pixel data to a video display.

Method and apparatus for producing a semi-transparent cursor on a data

Encoded color image data, stored in a first format such as YUV or YIQ, is converted to RGB format for output to a color display system. The conversion is carried out in real time synchronism with generation of the display, in order to minimize buffer storage requirements for the RGB output data. Present circuits use RAM (random access memory) storage arrays lookup tables for product functions defined in associated conversion equations. Each product function is a product of multiplication of a predetermined constant and data representing a U or V component of a source image pixel. Use of these tables effectively speeds up the conversion process, and has the added advantage of flexibility since the respective data is changeable to adjust to various image and display formats and conditions. In one embodiment, a RAM array used in the present format conversion process is also used (in a different display mode, with different stored data) as a conventional source of palette data. In the present conversion process, a cascaded network of adders receives product functions read out of one or more lookup table RAM arrays, adds certain of these functions together, and adds data representing Y components corresponding to the lookup table U and V arguments, to produce final output data representing red, green and blue (RGB) attributes of an instantly displayable pixel corresponding to a source pixel associated with respective source YUV components.

RAM based YUV-RGB conversion

A computer graphics and display system is provided, comprising (i) a graphics system for outputting a first plurality of digital color signals; (ii) a first digital-to-analog converter (DAC) for converting the first plurality of digital color signals into a second plurality of analog color signals, the second plurality being less in number than the first plurality; (iii) a first analog-to-digital converter (ADC) for reconverting the second plurality of analog color signals back to the first plurality of digital color signals; and (iv) an LCD display device for receiving the reconverted first plurality of digital color signals. The first and second DACs and the first and second ADCs are implemented within the same integrated circuit (IC) chip. The first plurality of digital color signals comprises red, blue and green even pixels and red, blue and green odd pixels. Each color for both even and odd pixels is encoded onto a single pair of the first DACs by interleaving same color pixels onto the single pair.

Method and system for multiplexing and demultiplexing video signals for

The graphics display system comprises a data bus for transferring a set of application pixels, wherein a set consists of W number of blocks of data, and wherein each application pixel is M number of blocks. The graphics display system further comprises an address bus for transferring memory addresses, a graphics controller for outputting pixel data on the data bus at a rate of one set per memory clock cycle and for outputting one or more column addresses on the address bus for each set, and a graphics memory configured for a memory field size of N number of blocks such that an application pixel being stored is allocated N blocks. A set of application pixels is transferred over the data bus to the graphics memory, and, one or more column addresses are transferred over the address bus during the a memory clock cycle over the address bus. In addition, a row address is transferred to the graphics memory. Each block of the transferred set belongs to one of N/M groups of blocks, and each of these blocks are stored in the graphics memory in a memory field indicated by a transferred row and column address pair, wherein each group of blocks is stored at a different one of N/M number of column addresses for any given transferred set.

Method and system of updating graphics memory in a graphics display

A method and apparatus are provided for reducing the memory requirements of a decoding subsystem by storing reference frames in compressed form. A reference picture in a sequence is decoded, compressed and stored in memory. When the reference frame is needed for motion compensation, it is decompressed.

Approximate MPEG decoder with compressed reference frames

A method and apparatus for a computer graphics system identifies the format of video pixel data in a data stream having a plurality of data formats including a first pixel data format and a second pixel data format, the second pixel data format being a YUV format. The method comprises the steps of (a) receiving pixel data; (b) selecting an output channel in response to at least one particular value of at least one bit of each received pixel datum wherein the particular value identifies the data format as either the first pixel data format or the YUV format; and (c) providing the pixel data to the selected output channel. Also provided is a circuit in a video graphics controller and a computer system having such circuit according to the method.

Method for identifying video pixel data format in a mixed format data

A programmable serializer comprising a multi-bit input port, a multi-bit output port, at least one multiplexer and at least one programmable address counter corresponding to the multiplexer for generating a sequence of multiplexer data input addresses that are inputted into the multiplexer address input. The multiplexer has an output connected to the multi-bit output port, an address input and a plurality of data input channels having addresses. Each data input channel is connected to a corresponding bit of the multi-bit input port. At least one data input channel is coupled to the multiplexer output when the corresponding address of the data input channel is applied to the address input. The programmable address counter receives and stores an initial address value, an address increment value and a count value and generates a sequence of addresses based on these values. The initial address value represents the multiplexer data channel that is to be initially coupled to the multiplexer output. The address increment value represents the increment that must be added to a current address in order to reach a next address. The count value represents the number of address that must be generated by the counter prior to restarting the sequence at the initial address value.

Programmable serializer using multiplexer and programmable address

A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.

Self-timed real-time data transfer in video-RAM

A graphics display subsystem that allows rejection of double buffer display of pixel data in a graphics layer is provided. The subsystem has a memory containing a plurality of pixels represented by binary bits, wherein each pixel is divided into two or more sub-pixel fields, and wherein one or more bits of a particular sub-pixel field of a given pixel are set to a predetermined double buffer reject value when the given pixel corresponds to a single buffer display application. A double buffer reject circuit compares one or more bits of a double buffer sub-pixel field of a given pixel with a predetermined double buffer reject value to determine equality of the one or more bits and the predetermined value, wherein the given pixel is represented by binary bits and wherein the given pixel is divided into two or more sub-pixel fields including the double buffer sub-pixel field. The double buffer reject circuit receives a buffer select signal selecting one of the two or more sub-pixel fields of the given pixel to be accessed during a current display frame. In response, the double buffer reject circuit accesses the selected sub-pixel field of the given pixel when the buffer select signal does not select the double buffer sub-pixel field or when the buffer select signal selects the double buffer sub-pixel field and the comparison does not show equality, and further the double buffer reject circuit accesses one of the two or more sub-pixel fields of the given pixel that is not the double buffer sub-pixel field when the buffer select signal selects the double buffer sub-pixel field and the comparison shows equality. A digital-to-analog converter in communication with the double buffer reject circuit receives the pixel data contained in the sub-pixel field accessed by the double buffer reject circuit and converts the pixel data into analog video signals for driving a monitor display device.

Graphics display subsystem that allows per pixel double buffer display

An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.

Memory structure with multiple integrated memory array portions

Video subsystem power savings are achieved by shutting off power to unused subcircuits during blanking. Digital circuitry within the video subsystem not used during blanking is shut-down by turning off the clock thereto. Analog circuitry within a digital to analog converter is shut-down by turning off the constant current reference thereto. A functional unit containing digital circuitry within a serializer palette digital to analog converter (SPDAC) is shut-down by turning off the clock thereto during system operation in a mode where the functional unit is not utilized. A computer system having a monochrome display saves power by shutting off DAC digital circuitry clocks and DAC analog circuitry constant current references of all DACs but one. A portable computer with a liquid crystal display (LCD), a SPDAC for driving an external display and a LCD controller, saves power by shutting down video subsystem functional units and analog DAC circuitry not used for driving the LCD. Digital circuitry within the LCD controller is shut-down when an external display is being driven. In a portable computer operating in a SUSPEND state, video subsystem functional units are shut-down.

Method and apparatus for power management in video subsystems

The presence or absence of a property in a computer subsystem is determined using a multiple input shift register (MISR). A subsystem device operates on predetermined test data to produce output data. The MISR operates on the output data to produce a final test value dependent on the output data. The property has a known final MISR value associated with the device under test and the test data. The MISR final test value is read and compared to the known final value for the property. If the two values are the same, the property exists in the system. In a second embodiment, a property from among a set of known possible properties or variations of a property is determined. In a specific application of the second embodiment, the length of a serial access memory (SAM) portion of a video random access memory (VRAM) is determined.

Method for determining computer subsystem property

Stored data for two different images superimposed on one another can be accessed simply and efficiently from the same VRAM. The SAM of the VRAM is divided into multiple-independent portions, each of which respond to its own independently controlled address counter. By loading the image data access into respective SAM portions, and switching data access between SAM portions at the SAM address rate, superimposed data of two different images can be displayed from the same VRAM.

Growing community of inventors

Colchester, VT, United States of America

Roderick Michael West