International Business Machines Corporation

Roderick M West

Todd Williams

Nicholas David Butler

Adrian C Gay

Matthew Damien Bates

Steven P Larky

Brian Clive Homewood

Vincent P Thomas

Malcolm Douglas Buttimer

Terence G Cole

Paolo G Sidoli

Jong H Kim

John P Woodley

In a logic circuit having clocked state latches and combinatorial logic for functional processing of a task in response to functional clocking of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic is provided for suspending task processing by interrupting the functional clocking of the state latches and, during such suspension, scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performed by a logic circuit in a multiprocessing enviornment.

Logic circuit for task processing

In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.

Memory with page mode

A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.

Video Random Access Memory serial port access

Video random access memory serial port access

A digital arithmetic logic unit in which the carry chain is subdivided into a series of bit fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit fields. Division of the carry chain is achieved via a carry chain selector consisting of a series of multiplexers, one being placed between each pair of adjacent stages of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of one bit field and provides the least significant carry-in bit to the next bit field. This selection of the carry by the multiplexer is under control of a programmable register, thus allowing variable division of the carry chain.

Arithmetic logic unit

Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic pulses applied to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be changed by differentially driving the cell write injectors over the bit lines. Output multiplexing of cells storing corresponding bit positions in the words is achieved simply by connecting the cell outputs together (dot ANDing). Logical output discrimination and interfacing is achieved by comparing the multiplexed output current with a threshold current. If the output current is less than the threshold current, the cell is storing a logical ONE. If the output current is greater than the threshold current, the cell is storing a logical ZERO.

MTL storage cell with inherent output multiplex capability

A step waveform generator includes a cup and bucket circuit in which charging and discharging a cup capacitor (C1) with predetermined units of charge is achieved, in response to a train of pulses supplied to its input terminal (1), by means of an operational amplifier (2) continuously monitoring the voltage across the cup capacitor and alternately supplying charging current and discharging current from a first and second constant current source (I1 and I2) respectively via separate feedback loops (T3, T2 and T4, T7, T6) of the amplifier. The constant currents, or multiples or sub-multiples of the constant currents, providing each individual unit of charge, are generated by current mirrors (T8, T9, T10) and added sequentially to a bucket capacitor C2. The size of each individual step of the resultant voltage waveform derived from the bucket capacitor and appearing at output terminal 4 depends upon the combination of mirrored increments of current selected by switch (S1, S2) and added to the bucket capacitor. The waveform generator is particularly useful when driven by CRT horizontal sync pulses to provide a vertical timebase circuit generating a stepped voltage waveform instead of the more customary ramp voltage waveform. Appropriate combination of the outputs of the mirrors by judicious operation of the switches S1, S2 controls field interlace and single and multiple line skips.

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Chandlers Ford, United Kingdom

Roderick M West