Nxp USA, Inc.

Roderick Lee Dorris

Michael Andrew Fischer

John David Round

An SoC includes an execution domain processor for running an execution domain which hosts n partitions by accessing, for each partition, one or more SoC resources; a control point processor that generates control data with n debug enable signals corresponding to the n partitions for controlling access to the SoC resources by identifying at least a first SoC resource that each partition is allowed to access; and an access control circuit to provide, in response to the control data, a dynamic runtime isolation barrier which allows access by the debugging tool to only a specified partition running on the execution domain which has a debug enable signal set to a first active value and prevents access to the other n−1 partitions running on the execution domain, For the partition under debug, the dynamic runtime isolation barrier may block debugger access to selected memory regions accessible by the partition under debug.

Multi-partition, multi-domain system-on-chip joint test action group (JTAG) debug control architecture and method

A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

System on chip with pre-exemption interrupts for partition execution control

A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain; a control point processor that is physically and programmatically independent from the execution domain processor and configured to generate control data for controlling access by the execution domain to one or more SoC resources by identifying at least a first SoC resource that the execution domain is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and including a programmable front end which is connected to receive the control data from the control point processor, and a signals-based back end which is configured to provide a dynamic runtime isolation barrier in response to the control data, thereby controlling access to the one or more system-on-chip resources by the execution domain.

Control channel architecture

A Remap Address Space Controller controls access to an address space by selectively remapping a physical address of a transaction received from a controller to form a remapped physical address according to a current execution context of the controller. The selective remapping is based on a determination of whether the current execution context of the controller allows the transaction to access the address space. Remap Address Space Controller selectively provides the transaction with the remapped physical address to a memory bus based on the determination of whether the current execution context of the controller allows the transaction to access the address space.

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Dripping Springs, TX, United States of America

Roderick Lee Dorris