Seagate Technology Incorporated

Rod V Bowman

Yong Lu

Yiran Chen

Hai Li

Harry Hongyue Liu

Daniel Seymour Reed

Haiwen Xi

Patrick Joseph Ryan

Brian Lee

Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

Bit set modes for a resistive sense memory cell array

Method and apparatus for tuning a variable resistance resistive sense element of an electronic device. In some embodiments, a value indicative of a selected number of consecutive pulses is stored in a memory location and a resistive sense element (RSE) is set to a baseline RSE resistance. A tuning operation is performed by applying the selected number of consecutive pulses to the RSE to tune the baseline RSE resistance to a final adjusted resistance.

Tuning a variable resistance of a resistive sense element

Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.

Computer memory device with multiple interfaces

Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array.

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Bloomington, MN, United States of America

Rod V Bowman