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Advanced Micro Devices Corporation

Rod Fleck

Karl-Heinz Mattheis

Mark Poret

Christoph Meinhold

Javier V Magana

Steffen Storandt

Werner Boening

A microprocessor assembly includes an integrated microprocessor and an external bus having a plurality of signal lines and a corresponding number of terminals connected to the integrated microprocessor. The integrated microprocessor includes a plurality of terminals; a core processor; at least one quasi-external bus having a plurality of signal lines; a bus control unit connecting the core processor to the quasi-external bus; a device connecting the quasi-external bus to the external bus through a corresponding number of terminals; and at least one peripheral connected to the quasi-external bus. The quasi-external bus has at least the same number of signal lines carrying the same signal as the external bus, and the quasi-external bus has the same control performance as the external bus, for connecting a peripheral without modification to both the external bus and the quasi-external bus.

Integrated microprocessor with internal bus and on-chip peripheral

An apparatus for furnishing instructions having a multi-stage pipeline processing unit for processing at least a 'fetch instruction' phase, a 'decode instruction' phase and an 'execute instruction' phase, includes a memory; an address register having contents pointing to an instruction to be processed in said memory; an instruction register for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit for calculating addresses; an incrementing stage for incrementing the contents of said address register; and a multiplexer for selecting a calculated address or an incremented successor address. One embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit. Another embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit.

Apparatus for furnishing instructions in a microprocessor with a

A circuit configuration and a method for priority selection of interrupts for a microprocessor in an integrated circuit which includes a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for presenting interrupt requests to the central processing unit, peripheral interrupt nodes each being connected to a respective one of the N interrupt sources. A common interrupt bus is connected to the peripheral interrupt nodes and to the central interrupt node. The method for priority selection includes activating the interrupt bus in a prioritizing round in accordance with a priority value with a peripheral interrupt node assigned to an interrupt source in the presence of an interrupt request of the interrupt source.

Circuit configuration and method for priority selection of interrupts

A circuit configuration for improving the resolution of successive pulsed signals over time includes first and second counters each having one clock input, the clock input of the first counter being supplied with a first clock signal, and the clock input of the second counter being supplied with a second clock signal having a n-multiple frequency of the first clock signal. The first counter has a control input and a counter output, the control input of the first counter being supplied with successive pulsed signals. The second counter has a counter input, an overflow output and a write input, the write input of the second counter being connected to the overflow output of the second counter. A register has a data input, a data output, and a write input, the data input of the register being connected to the counter output of the first counter, the write input of the register being connected to the control input of the first counter, and the data output of the register being connected to the counter input of the second counter. The counter state of the first counter is written into the register through the counter output of the first counter and the first counter is subsequently reset, upon one of the successive pulsed signals being supplied to the control input of the first counter. The second counter assumes the value of the register when an overflow signal is tripped.

Circuit configuration for improving the resolution of successive pulsed

A counter/timer circuit for a microcontroller includes a central register and two auxiliary registers each having transfer outputs and counting inputs. Bistable output storage elements are each connected to a respective one of the transfer outputs. Interrupt request flags are also each connected to a respective one of the transfer outputs. Start/stop elements are each connected to a respective one of the counting inputs. Input control blocks are each connected to a respective one of the start/stop elements. First reload, capture and compare units are connected between one of the auxiliary registers and the central register, and second reload, capture and compare units are connected between the other of the auxiliary registers and the central register.

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Munich, Germany

Rod Fleck