Micron Technology Incorporated

Micron Semiconductor, Inc.

Rod C Langley

Howard E Rhodes

Timothy P O'Brien

William J Crane

Robin Lee Gilchrist

Alan J Lamberton

Curtis S Jones

A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90&#xb0; from horizontal, with no bowing or notching.

Anisotropic etch method

A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90&deg; from horizontal, with no bowing or notching.

A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.

A semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner conductive node and an elevationally outer conductive node includes, a) providing an inner node location to which electrical connection is to be made; b) providing an electrically insulative layer outwardly over the inner node location; c) patterning and etching a contact opening through the insulative layer to the inner node location; d) substantially filling the contact opening with an electrically conductive material to provide a conductive plug within the contact opening to the inner node location, the conductive plug defining an outermost fang gap between the conductive plug and the electrically insulative layer, the fang gap having a first width; e) widening the fang gap to a second width which is greater than the first width by a timed RF plasma etch of the electrically conductive material; f) providing an outer metal layer over the conductive plug after the widening step, the metal layer at least partially filling the widened fang gap; and g) patterning the metal layer into a conductive line which electrically interconnects with the conductive plug.

Semiconductor processing method of providing an electrically conductive

In one aspect, a semiconductor processing method for connecting a metal layer to a plug when there is a fang gap between the plug and a layer surrounding the plug includes: a) forming a conductive material within an opening in a surrounding layer; b) etching the conductive material with a first etch chemistry to form a fang gap between the conductive material and the surrounding layer, the fang gap having a first width; c) etching the conductive material with a second etch chemistry to widen the fang gap to a second width which is greater than the first width, the second etch chemistry being different from the first etch chemistry; and d) providing an outer metal layer over the conductive plug after widening the fang gap, the metal layer at least partially filling the widened fang gap.

There is a post etching test apparatus and method to be able to only test just a few die on the wafer. Uniquely, the remainder of the die on the wafer can be salvaged, if the test identifies proper tolerances for the etching process over the entire wafer surface. If the tests show negative, the etch process can be re calibrated and the wafer can be reprocessed and tested again. Salvage of the majority of the die on the wafer under test is possible by using a fine point resist removal plate. Specifically, oxygen is forced over certain die on the wafer to remove the resist mask by using a plate barrier with only a few holes in it. The holes are located a key positions around the wafer, and restrain the oxygen laminar flow to effect only the wafers directly below these holes.

After etch test method and apparatus

The process of the present invention comprises the addition of an adequate amount of argon gas in a dry etch system to clear bond pads of residual contaminants which form an undesired oxide coating on the bond pads. Carbon dioxide may be used as a carrier gas along with the argon gas. The process of the present invention preferably takes place in situ, following the silicon nitride pad etch in which fluorine-containing chemicals are used to form the bond pads.

Method to remove fluorine residues from bond pads

A method to anisotropically etch an oxide/metalsilicide/polysilicon sandwich structure on a silicon wafer substrate in situ, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a metalsilicide/polysilicon etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.

A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step that utilizes C.sub.2 F.sub.6, CF.sub.4, CHF.sub.3 and an inert carrier gas as the etching atmosphere. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.

A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step, both of which are performed as plasma etch steps. The process allows a continuous etch to be applied without removing the wafer from the plasma reactor chamber. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.

A self-aligned, sloped contact, through BPSG and thick TEOS (at least 200 nm but preferably 300-500 nm or more). Sloping is achieved through exploitation of BPSG and TEOS etch characteristics, to independently form concave and convex sidewalls, respectively. Self-alignment is obtained through thick conformal TEOS, along a sidewall of an underlying structure such as a transistor gate, directing contact formation away from the structure. TEOS etch is timed, allowing simultaneous formation of contacts to substrate and gates without overetching gates.

Self-aligned sloped contact

The present invention is a contact etch method which simultaneously smoothes a reflowed oxide profile so that separate phanarization photoresist coat and etch steps are unnecessary. This method is characterized in that it is fast, uses only one photoresist mask layer, etches contacts to poly and to substrate simultaneously, is done entirely with plasma etch technology in a single reactor, and builds up less polymer in the plasma reactor. The novel method eliminates a coat and an etch step, improving yield and reducing fabrication time. Lower polymer buildup means higher yields due to a cleaner process, and less downtime for reactor chamber cleaning.

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Boise, ID, United States of America

Rod C Langley