International Business Machines Corporation

Roch Georges Archambault

Yaoqing Gao

Raul Esteban Silvera

Shimin Cui

Robert J Blainey

Peng Zhao

Francis Patrick O'Connell

James Lawrence McInnes

Allan Russell Martin

Steven Wayne White

Mark Peter Mendell

Stephen Curial

Alexandre E Eichenberger

Robert Brett Tremaine

Lixin Zhang

Peng Wu

Geoffrey Owen Blandy

Ronald Ian McIntosh

Randall Ray Heisch

Guansong Zhang

Robert F Enenkel

Michael Edward Wazlowski

Chengliang Zhang

Maria Eleftheriou

Pascal Vezolle

Chen Ding

Charles Brian Hall

Siddhartha Chatterjee

Robert William Hay

Edwin Chan

John David McCalpin

Liangxiao Hu

Anthony Simon Bolmarcich

Zhixing Ren

Graham K Yiu

Raymond Mak

Roland Froese

Erik P Charlebois

Xiaoming Gu

Yaoging Gao

Yingwei Zhang

G Calin Cascaval

George Chochia

Amy Kai-Ting Wang

Graham Yiu

Embodiments of the present invention provide a method, system and computer program product for the data splitting of recursive data structures. In one embodiment of the invention, a method for data splitting recursive data structures can be provided. The method can include identifying data objects of a recursive data structure type, such as a linked list, within source code, the recursive data structure type defining multiple different data fields. The method further can include grouping the data objects into some memory pool units, each of which can contain the same number of data objects. Each memory pool unit can be seen as an array of data objects. The method can include data splitting, which could be maximal array splitting in each different memory pool unit. Finally, the method can include three different approaches, including field padding, field padding and field splitting, to handle irregular field sizes in the data structure.

Data splitting for recursive data structures

A code region of an application is instrumented by a multi-pass profiler with first annotations for generating profile data. The application is executed with the first annotations, wherein executing the application with the first annotations generates first profile data for the code region. The multi-pass profiler identifies, from the first profile data, the code region as a delinquent code region. The multi-pass profiler determines second annotations based, at least in part, on the first profile data and the at least one of the first annotations that defines the delinquent code region. The multi-pass profiler instruments, based on the first profile data, a code sub-region of the delinquent code region with the second annotations for generating profile data. The application is executed with second annotations, wherein executing the application with the second annotations generates second profile data for the code sub-region.

Multiple pass compiler instrumentation infrastructure

The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.

Method and apparatus for software-assisted data cache and prefetch control

May-constant propagation is a technique used to propagate a constant through the call graph and control flow graph by ignoring possible kills and re-definitions with low probability. Variables associated with constants in program code are determined. Execution flow probabilities are executed for code segments of the program code that comprise the variables. The execution flow probabilities are calculated based on flow data for the program code. At least a first of the code segments is determined to have a high execution flow probability. The first of the constants associated with the first variable are propagated through the flow data to generate modified flow data.

May-constant propagation

A computer implemented method, apparatus, and computer usable program code for compiling source code for performing a complex operation followed by a complex reduction operation. A method is determined for generating executable code for performing the complex operation and the complex reduction operation. Executable code is generated for computing sub-products, reducing the sub-products to intermediate results, and summing the intermediate results to generate a final result in response to a determination that a reduced single instruction multiple data method is appropriate.

Code generation for complex arithmetic reduction for architectures lacking cross data-path support

A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.

Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations

Computer implemented method, system and computer usable program code for cache management. A cache is provided, wherein the cache is viewed as a sorted array of data elements, wherein a top position of the array is a most recently used position of the array and a bottom position of the array is a least recently used position of the array. A memory access sequence is provided, and a training operation is performed with respect to a memory access of the memory access sequence to determine a type of memory access operation to be performed with respect to the memory access. Responsive to a result of the training operation, a cache replacement operation is performed using the determined memory access operation with respect to the memory access.

Optimal cache replacement scheme using a training operation

A computer implemented method for facilitating debugging of source code. The source code is scanned to identify a candidate region. A procedure control descriptor is generated, wherein the procedure control descriptor corresponds to the candidate region. The procedure control descriptor identifies, for the candidate region, a condition which, if true at runtime means that the candidate region can be specialized. Responsive to a determination during compile time that satisfaction of at least one condition will be known only at runtime, the procedure control descriptor is used to specialize the candidate region at compile time to create a first version of the candidate region for execution in a case where the condition is true and a second version of the candidate region for execution in a case where the condition is false, and further generate code to correctly select one of the first region and the second region at runtime.

Procedure control descriptor-based code specialization for context sensitive memory disambiguation

A target operation in a normalized target loop, susceptible of vectorization and which may, after compilation into a vectorized form, seek to operate on data in nonconsecutive physical memory, is identified in source code. Hardware instructions are inserted into executable code generated from the source code, directing a system that will run the executable code to create a representation of the data in consecutive physical memory. A vector loop containing the target operation is replaced, in the executable code, with a function call to a vector library to call a vector function that will operate on the representation to generate a result identical to output expected from executing the vector loop containing the target operation. On execution, a representation of data residing in nonconsecutive physical memory is created in consecutive physical memory, and the vectorized target operation is applied to the representation to process the data.

Sparse vectorization without hardware gather/scatter

Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a computer system, the method including building a control flow graph, identifying both countable and non-countable loops, gathering a set of candidate loops for load speculation, and for each candidate loop in the set of candidate loops gathered for load speculation, computing an estimate of the iteration count, delay cycles, and code size, performing a profitability analysis and determining an unroll factor based on the delay cycles and the code size, transforming the loop by generating a prologue loop to achieve data alignment and an unrolled main loop with loop directives, indicating which loads can safely be executed speculatively and performing low-level instruction scheduling on the generated unrolled main loop.

Systems, methods, and computer products for compiler support for aggressive safe load speculation

A method of compiling source code. The method includes converting pointer-based access in the source code to array-based access in the source code in a first pass compilation of the source code. Information is collected for objects in the source code during the first pass compilation. Candidate objects in the source code are selected based on the collected information to form selected candidate objects. Global stride variables are created for the selected candidate objects. Memory allocation operations are updated for the selected candidate objects in a second pass compilation of the source code. Multiple-level pointer indirect references are replaced in the source code with multi-dimensional array indexed references for the selected candidate objects in the second pass compilation of the source code.

Compiling source code

Inter-procedural strength reduction is provided by a mechanism of the present invention to optimize software program. During a forward pass, the present invention collects information of global variables and analyzes the information to select candidate computations for optimization. During a backward pass, the present invention replaces costly computations with less costly or weaker computations using pre-computed values and inserts store operations of new global variables to pre-compute the costly computations at definition points of the global variables used in the costly computations.

Method and apparatus for optimizing software program using inter-procedural strength reduction

A method for implementing architecture cloning including: constructing a program call graph in a link phase of interprocedural analysis to model calling relationships between one or more procedures in a program; analyzing the program call graph to obtain information about the program; analyzing the program to identify the one or more procedures subject to architecture cloning; determining feasibility of architecture cloning; marking the one or more procedures in the program suitable for architecture cloning; naming the one or more procedures in the program suitable for architecture cloning; inserting a runtime routine call at an entry point of the program; invoking architecture cloning when one or more candidate procedures are identified during procedure cloning; providing a user with an interface for specifying multiple architecture targets to the compiler; and enabling the compiler to generate architectural specific instructions optimized for each of the multiple architecture targets.

Architecture cloning for power PC processors

A method for implementing shadow versioning to improve data dependence analysis for instruction scheduling in compiling code, and to identify loops within the code to be compiled, for each loop initializing a dependence a matrix, for each loop shadow identifying symbols that are accessed by the loop, examining dependencies, storing, comparing and classifying the dependence vectors, generating new shadow symbols, replacing the old shadow symbols with the new shadow symbols, generating alias relationships between the newly created shadow symbols, scheduling instructions and compiling the code.

Implementing shadow versioning to improve data dependence analysis for instruction scheduling

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North York, Canada

Roch Georges Archambault