United States of America As Represented by the Secretary of the Air Force

Icf International

Robinson E Pino

James W Bohl

Qing Wu

Youngok Pino

Garrett Rose

Michael J Shevenell

Lee C Trossbach, Jr

A system that collects data from monitored network traffic. The system inputs, in parallel, the data through inputs of a neural network. The system compares an output of the neural network, generated in response to the inputted data, to at least one predetermined output. If the output of the neural network corresponds to the at least one predetermined output, the system provides a notification relating to the data.

Method and apparatus for monitoring network traffic

A method and apparatus can be configured to perform the steps of displaying, on a display, a first visual representation of volume in three-dimensional space. The method can also display, on the display, a visual representation of a network security alert. The network security alert can correspond to a notification of a network attack, a network intrusion, or an unwanted activity. The representation of the network security alert can be positioned within the first visual representation of volume. The position of the representation of the network security alert within the first visual representation of volume reflects at least one characteristic of the network security alert.

Method and apparatus for visualizing network security alerts

CMOS-memristor circuit is constructed to behave as a trainable artificial synapse for neuromorphic hardware systems. The invention relies on the memristance of a memristor at the input side of the device to act as a reconfigurable weight that is adjusted to realize a desired function. The invention relies on charge sharing at the output to enable the summation of signals from multiple synapses at the input node of a neuron circuit, implemented using a CMOS amplifier circuit. The combination of several memristive synapses and a neuron circuit constitute a neuromorphic circuit capable of learning and implementing a multitude of possible functionalities.

Electronic charge sharing CMOS-memristor neural circuit

An apparatus for reconfigurable computing logic implemented by an innovative memristor based computing architecture. The invention employs a decoder to select memristor devices whose ON/OFF impedance state will determine the reconfigurable logic output. Thus, the resulting circuit design can be electronically configured and re-configured to implement any multi-input/output Boolean logic computing functionality. Moreover, the invention retains its configured logic state without the application of a current or voltage source.

Reconfigurable memristor-based computing logic

A neuromorphic computing device utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. The invention provides advantages over software-based neuromorphic computing methods.

Neuromorphic computer

An apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices. The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change. Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed.

Self-reconfigurable memristor-based analog resonant computer

A method and apparatus for modeling the characteristics of memristor devices. The invention provides methods and an apparatus for accurately characterizing the linear and non-linear Lissajous current-voltage behavior of actual memristor devices and incorporating such behavior into the resultant model. The invention produces a model that is adaptable to large scale memristor device simulations.

Method and apparatus for modeling memristor devices

An apparatus and method provides the foundation for designing reconfigurable electronic computing systems. The invention relies on an ability to change the resistance state of a memristor device to achieve an optimal voltage at specific circuit nodes, whereby this dynamically and autonomously causes the circuit to reconfigure itself and produce a different output for the same input relative to the circuit's initial state. The circuit's state remains constant until the memristor's resistance is changed, at which point the circuit's function is 'reprogrammed'.

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Rome, NY, United States of America

Robinson E Pino