Motorola Corporation

Robin W Edenfield

William B Ledbetter, Jr

Russell A Reininger

Ralph C McGarity

Van B Shahan

Eric E Quintana

A data processor is provided for reloading deferred pushes in copy-back cache. When a cache 'miss' occurs, a cache controller selects a cache line for replacement, and request a burst line read to transfer the required cache line from an external memory. When the date entries in the cache line selected for replacement are marked dirty, the cache controller 'pushes' the cache line or dirty portions thereof into a buffer, which stores the cache line pending completion, by a bus interface controller, or the burst line read. When the burst line read terminates abnormally, due to a bus error or bus cache inhibit (or any other reason), the data cache controller reloads the copy-back cache with the cache line stored in the buffer. The reloading of the copy-back cache avoids the potential for multiple concurrent exception conditions, and eliminates the problem of unnecessarily removing an otherwise valid cache entry from the cache.

Data processor for reloading deferred pushes in a copy-back data cache

A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allows the programmer to fully utilize the maximum bus bandwidth of the system bus for memory to memory transfers of data (e.g. DMA, block moves, memory page initialization) and transfers of instructions/data to detached coprocessors.

Data processing system utilizes block move instruction for burst

A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (dirtiness). Multiple dirty bits provide a data cache controller with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory. The portions of the entry being replaced that are clean (unmodified) are not written to memory.

System for transferring selected data words between main memory and

A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.

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Austin, TX, United States of America

Robin W Edenfield