Advanced Micro Devices Corporation

Applied Materials, Inc.

Unity Semiconductor Corporation

Other

Apple Inc.

Amd Inc.

Robin W Cheung

Richard J Huang

Ratson Morad

Steven C Avanzino

Yezdi N Dordi

Mark S Chang

Darrell M Erb

Ho Seon Shin

Darrell Rinerson

Ashok K Sinha

Sergey D Lopatin

Simon S Chan

Jonathan Bornstein

David Hansen

Peter W Hey

Ming-Ren Lin

Rich K Klein

Igor G Kogan

Hugo W Chan

Paul Raymond Besser

Avi Tepman

Subhash Gupta

Seshadri Ramaswami

Dan Carl

Travis Byonghyop Oh

Minh Van Ngo

Angela Tai Hui

Liang-Yuh Chen

Lu You

Scott D Luning

Dan A Marohl

Michael N Sugarman

Lewis N Shen

Chiu H Ting

Donald J Olgado

Daniel A Carl

Richard K Klein

Joseph Stevens

Paul F Smith

Mark Robert Denome

Bryan M Tracy

George Birkmaier

Eugene Ravinovich

Fei Wang

Takeshi Nogami

Srinivas Gandikota

Valery M Dubin

Barry Lee Chin

Steven W Longcor

Girish Anant Dixit

Suketu Arun Parikh

Lawrence Schloss

Guarionex Morales

Rene Meyer

Raymond T Lee

Sivakami Ramanathan

Rajat Rakkhit

Hsiang-Wen Chen

Mark Lloyd

Bernard W Ho

David F Kyser

Wen Zhong Kong

Pervaiz Sultan

Sheshadri Ramaswami

Charles E May

Imran Hashim

Deenesh Padhi

Peijun Ding

Christy Mei-Chu Woo

Fusen E Chen

John A Iacoponi

Yu Albert Wang

Liang Light Chen

James Jiahua Yu

Siyi Li

Michael J Wood

Dennis J Yost

Zachary Michael Beiley

Moon-Yee Wang

Jennifer Meng Tseng

Hugo W-k Chan

John S Lewis

Chris R McGuirk

Muhammad Atif Malik

Hong-Gee Fang

Robert Chen

Yu-Hua Chang

Richard W Snow

Anna Marie Lloyd, Legal Representative

John H Madok

B Michelle Chen

A method for fabricating an optoelectronic device includes forming an isolation structure between an array of pixel electrodes and a built-in pad (BIP) on a dielectric layer of an integrated circuit, depositing a photosensitive film over the dielectric layer, such that at least one pinch point is formed in the photosensitive film at an edge of the isolation structure. The method further includes depositing an electrode layer, which is at least partially transparent, over the photosensitive film, etching away the photosensitive film from the BIP, and after etching away the photosensitive film, depositing a metal layer over the BIP and in contact with the electrode layer.

Isolation structures in film-based image sensors

A multi-touch remote control method comprises following steps: a remote control device receiving a touch gesture input; computing a number of the touch points of the touch gesture input; generating and transferring a mouse event data to a receiving device as a mouse input if the number of the touch points is 1; and generating and transferring a single touch event data to the receiving device as a single touch input if the number of the touch points is greater than 1 and all the touch points of the touch gesture input are close to each other.

Multi-touch remote control method

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Device fabrication

A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 &#x212b;. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Immersion platinum plating solution

Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO, LaSrCoO, LaNiO, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Memory device using ion implant isolated conductive metal oxide

A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Continuous plane of thin-film materials for a two-terminal cross-point memory

Memory cell formation using ion implant isolated conductive metal oxide

The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.

Electro-chemical deposition system

Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.

Methods for post-etch deposition of a dielectric film

A method and apparatus for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufacturing facility where the design release is used for producing the layout of the integrated circuit and the design intent information is coupled to the equipment, especially the metrology equipment, within the IC manufacturing facility. As such, the design intent information can be used to optimize processing during IC fabrication to achieve optimization of the critical characteristics intended by the designer.

Method and apparatus for capturing and using design intent in an integrated circuit fabrication process

Growing community of inventors

Cupertino, CA, United States of America

Robin W Cheung