Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.P.

Robin T Tran

Christopher E Simonich

Michael R Durham

Mark A Piwonka

Lee B Hinkle

Michael A Wright

The preferred embodiment of the invention has a combination of a detection circuit and executable software. The detection circuit is capable of detecting the removal and replacement of a computer system microprocessor and latching an indication that the microprocessor has been removed, even if that removal has taken place while the computer system is without power. Having latched an indication that the microprocessor has been removed and replaced, the detection circuit asserts appropriate signals to start the microprocessor in a safe mode. Once operating in a safe mode, an executable program polls the latched indication, and if the indication is that the CPU has been removed and replaced, the software is further adapted to prompt a computer system user for a new host bus to CPU core speed ratio and modify registors to indicate a new value, if necessary, that are subsequently used to start the CPU at the correct operational speed.

Structure and method for automatically setting the CPU speed

A computer system which includes an electromagnetic hoodlock, and does not have any simple way to bypass the hood-lock The hoodlock consists of a spring-loaded solenoid, and is controlled by the system microprocessor. The system chassis may only be opened by a user with sufficient rights, after entering a password, or after an administrative command is sent over the computer network.

Electronic hood lock

A security methodology and security logic for protecting Plug and Play computer system components from unauthorized access. The security logic prevents modification of the base addresses of specified Plug and Play computer system components by blocking writes to specific index locations programmed into security registers. In the disclosed embodiment of the invention, the base address of a Super I/O chip is protected, as well as the base addresses of specified logical devices in the Super I/O chip. Protecting the base addresses in this manner prevents the security logic from being circumvented by interfering with the address decoding used to track reads and writes to protected index registers. In addition, the security registers are programmed to prevent access to the protected index registers of the logical devices.

Security methodology for devices having plug and play capabilities

In a personal computer system utilizing both a main power supply and an auxiliary power supply, the input and output signal lines of auxiliary powered components are selectively isolated from components powered solely by the main power supply. Gating circuitry and buffer circuitry, controlled by various enable signals, are used to isolate the signal lines. External pull-down or pull-up resistors are no longer required, which frees up printed circuit board area for other components and conserves board space in the computer system.

Personal computer component signal line isolation for an auxiliary powered component

A computer system is provided with a multifunction power switch. In addition to the normal function of turning the computer on and off, the power switch has the additional function of clearing CMOS memory. In one embodiment, pressing the power switch while the computer is connected to a power source turns the computer on and off, and when the computer is disconnected from the power source, the CMOS memory may be cleared by pressing and holding the power switch for a predetermined time delay, e.g. 10 seconds. As a precaution against malicious clearing of CMOS memory, activation of this feature may be disabled as long as the computer cover is closed. In this case, the computer cover would have to be at least partially removed before the power button is pressed and held to clear CMOS. An LED may be provided which illuminates to indicate the success of the CMOS clearing operation. Adding this functionality to the power button advantageously simplifies an otherwise difficult process for restoring a computer with corrupted CMOS to a bootable configuration.

Method and apparatus for restoring a computer to a clear CMOS configuration

A PCI-based computer system is provided with an expanded number of PCI master devices, in effect a second level of PCI arbitration. The expansion is made available without requiring additional bridge chips. Multiple PCI devices may arbitrate for control of the PCI bus via the primary PCI bus controller without requiring a specifically assigned signal pair, yet appear to system software to reside on the primary PCI bus.

Computer system for supporting increased PCI master devices without the requiring additional bridge chips

A run-time security methodology and apparatus for supporting complete access to the security features of a network computer by a network administrator. In a network computer according to the invention, various resources are secured by a security device. The resources are accessible by a computer user with knowledge of one or more user passwords stored in the security device. An administrator password is also stored in the security device. In addition to control access to specified resources, the administrator password also functions as a surrogate for the other passwords stored in the security device. An administrator password implemented according to the invention thereby allows a network administrator to remotely override any activated user security settings and receive complete access to a secured network computer.

Method and apparatus for providing remote access to security features on

A security device and methodology that prevents unauthorized access to general purpose I/O pins in a computer system. In a system according to the invention, secure general purpose I/O pins are utilized as enable signals for data transfer devices such as Universal Serial Port (USB) ports. In one embodiment of the invention, access to the secure general purpose I/O pins is governed by an administrator password that is protected by a memory slot in a security device. When an administrator (or other authorized user) desires access to the general purpose I/O register that controls the secure general purpose I/O pins, the administrator enters the administrator password. If the password is correct, the relevant slot of the security device is unlocked, thereby permitting completion of write cycles to the secure general purpose I/O register. If a write cycle to the secure general purpose I/O register is attempted while the relevant slot in the security device is locked, the write cycle is ignored. Control and monitoring of various system resources in a secure manner is thereby permitted via use of the secure general purpose I/O pins.

Secure general purpose input/output pins for protecting computer system

When a computer system's power button is depressed a timer is begun, an operating system visible status flag is set, and an interrupt is sent to the operating system indicating power button activation. If the operating system does not clear the flag within a specified time period, the computer system is considered to be in an error (e.g., 'hung' state) and the computer system is powered down.

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Houston, TX, United States of America

Robin T Tran