Cirrus Logic Inc.

Genesis Microchip Corporation

Cirrus Logtic, Inc.

Robin Sungsoo Han

Alexander Julian Eglit

Sridhar Kotha

Vlad Bril

Rakesh Kumar Bindlish

Ken Fuiks

Muralidhar Reddy Jammula

Vald Bril

A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.

Method and apparatus for providing LCD panel protection in an LCD display controller

A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data 'tag' (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g., LCD and CRT) are provided to temporarily store video data. FIFO pointers are fed back to a sequence controller to drive data read cycles from display memory. The use of tags and FIFO pointer feedback allows two video displays to be driven at different data rates, allowing for independent resolution and refresh rates in each display.

Dual displays having independent resolutions and refresh rates

A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA.TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.

Method and apparatus for expanding graphics images for LCD panels

A digital display unit receiving a display signal with image encoded at high origin frequencies (e.g., dot clock). A display signal interface samples the display signal during source display time to generate pixel data elements representative of the images encoded in the display signal. The signal is sampled at a sampling frequency equal to origin frequency. The pixel data elements are stored in a buffer at the sampling frequency and retrieved at a slower frequency. Display signals are generated for each horizontal scan line of a digital display screen during a destination display time at this slower frequency. The destination display time is designed to be longer than the source display time, which enables the display signals to be generated from all pixel data elements. The destination display time is longer than the source display time because digital display units do not require the long non-display times present in the display signals.

Method and apparatus for scanning a digital display screen of a computer

An apparatus for controlling a flat panel display with reduced flicker, particularly during grey scale shading. Three shading pattern lookup tables are provided, one for each sub-pixel color (Red, Blue, Green). Each shading pattern lookup table outputs a plurality of shading pattern duty cycle signals, each representing a different shade level. The phase of the three duty cycle signal patterns may be altered by adding a predetermined offset amount to one or more of the shading pattern lookup table addresses. By altering the phases of the outputs of the shading lookup tables, peak current demand within the flat panel display may be reduced and flicker or strobing of individual pixels may be reduced or eliminated.

Method and apparatus for reducing flicker in shaded displays

In a flat-panel display device, the ON/OFF duty cycle of each picture element of the array of picture elements is modulated during a multi-frame display sequence according to attribute information of respective picture element data to be displayed. The timing of ON/OFF and OFF/ON state transitions (i.e., the modulations) of the picture elements are coordinated within predetermined neighborhoods throughout the array of picture elements such that the state transitions occur substantially uniformly in space and time within a display neighborhood during the multi-frame display sequence. Advantage is taken of the visual averaging property by causing state transitions to occur substantially uniformly in space and time within each neighborhood throughout the array of picture elements during a multi-frame display sequence. Individual state transitions, which by themselves constitute display noise, are not perceived; instead, a coherent pattern of state transitions blending is provided that effectively simulates non-monochrome image displays. Dithering techniques are applied to realize a greater number of display colors than would otherwise be possible using conventional color LCD displays.

Process for producing shaded colored images using dithering techniques

A process for producing a wide range of shades in images that are presented in successive frames on image fields on opto-electronic display means having at least one illumination element at each of a plurality of pixel locations. Each pixel location, for example, may have a red, a green and a blue illumination element. The display is divided into uniformly-sized display neighborhoods. The process includes, for a given pixel location within any one of the uniformly-sized display neighborhoods, producing a given shade at that pixel location by selecting a frame sequence for illuminating the illumination elements at the pixel location during presentation of an image wherein the number of times that any given illumination element at the pixel location is illuminated within a given frame sequence is controlled to create an appearance of shading of that pixel location relative to other pixel locations and wherein adjacent pixel locations that have the same shade within any one of the display neighborhoods have their illumination elements illuminated with different frame sequences to minimize display noise.

Apparatus and method for producing shaded images on display screens

Shaded or color images are simulated using frame modulation techniques on flat panel displays having an array of binary display elements, i.e., display elements that have only two display states, an ON state and an OFF state. The timing of ON/OFF and OFF/ON state transitions of picture elements within predetermined neighborhoods through the array of display elements is coordinated such that the state transitions occur substantially uniformly in space and time during a multi-frame display sequence. Using a multi-frame sequence 16 frames in duration, 16 shades of gray may be realized on a monochrome display. The number of shades may be increased to 64 using dynamic dithering. Dithering is applied by causing the multi-frame sequence to be 64 frames in duration and dividing the multi-frame sequence into four sub-sequences each 16 frames in duration with the duty cycle of each display element during each of the four 16-frame sub-sequences being allowed to assume one of two adjacent values only such that display noise is minimized. The method may be applied to color displays in which pixel locations have illumination elements each of a different color, for example a red illumination element, a green illumination element and a blue illumination element.

Dithering process for producing shaded images on display screens

A method and apparatus for horizontally and vertically positioning a video graphics adapter (VGA) display image on the screen of a flat panel display (FPD) is provided with a first counter for setting a horizontal FPD disable period associated with the FPD. A second counter sets the horizontal FPD enable period of the FPD. This horizontal FPD enable period is greater than a composite horizontal pixel time of a VGA image to be displayed. A first circuit controls the start time of a subsequent horizontal FPD enable period. This start time is based on the horizontal FPD disable period. A second circuit controls the end time of the subsequent horizontal FPD enable period. This end time is based on the horizontal FPD enable period. The VGA display image is begun based on the start time of the subsequent horizontal FPD enable period to locate the VGA display image at a desired horizontal position of the FPD screen. The vertical positioning of the image is performed by similar counters and circuits.

Apparatus and method for horizontally and vertically positioning a VGA

A method and apparatus for expanding a video graphics adapter (VGA) text character to fully fill the screen of a flat panel display. The present invention stores binary information representing a horizontal row of character text. A prescribed bit in the binary information may be set to determine whether to duplicate pixels associated with the binary information in either a horizontal or vertical direction. A circuit is provided to ensure that foreground and background characteristics of the graphics character text being expanded are consistent with the sent prescribed bit in the binary information.

Growing community of inventors

Saratoga, CA, United States of America

Robin Sungsoo Han