Hewlett-packard Company

Robin Purohit

Bent Stoevhase

Robert H Grant

David Book

Gregory T Sullivan

Kumar Mallavalli

A fiber optic switch interconnects fiber optic channels so that a fiber optic network can be implemented. Channel modules provide ports (p1-pi) for connection of the fiber optic channels. Each channel module has a receive memory for temporarily storing incoming data frames from the fiber optic channels associated therewith. A switch module having a data distribution network interconnects each of the channel modules and permits ultimate connection of a source channel to a destination channel. A path allocation system, which controls the switch module, allocates the data paths between the channels. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the channels, a sentry which determines when a new data frame is ready to be routed, and an arbitrator which arbitrates port availability and which grants transfer requests proposed by the scheduler.

High performance path allocation system and method for a fiber optic

A fiber optic switch interconnects fiber optic channels so that a fiber optic network can be implemented. Channel modules provide ports (p1-pi) for connection of the fiber optic channels. Each channel module has a receive memory for temporarily storing incoming data frames from the fiber optic channels associated therewith. A switch module having a data distribution network interconnects each of the channel modules and permits ultimate connection of a source channel to a destination channel. A path allocation system, which controls the switch module, allocates the data paths between the channels. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the channels, a sentry which determines when a new data frame is ready to be routed, and an arbitrator which arbitrates port availability and which grants transfer requests proposed by the scheduler. Significantly, the arbitrator is equipped with fairness insurance mechanisms for insuring that transfer requests are always timely and efficiently serviced.

High performance path allocation system and method with fairness

A system for facilitating data communications in a fiber channel network is presented. The system comprises a fiber optic switch element which enables implementation of a Fiber Channel network by permitting selective interconnection of a plurality of fiber optic channels. The fiber optic switch element permits both circuit and frame switching. The switch element comprises a switch module which is connected to at least one fabric-port within the fiber channel fabric. The switch module allocates switching bandwidth. A path allocation system, which is connected to the switch module, generally directs frames of data between the at least one fabric-port to other fabric-ports located within the fabric. A channel module comprising a port intelligence mechanism is disposed between the switch module and the fabric-ports. An element controller provides centralized fabric management.

Switch element for fiber channel networks

A fiber optic switch interconnects ports (p1-pi) for connection with respective fiber optic channels so that a fiber optic network is realized. Channel modules provide the ports. Each channel module has a port intelligence mechanism for each port and a memory interface system for temporarily storing data passing to and from the ports. A switch module having a main distribution network, an intermix distribution network, and a control distribution network interconnects the memory interface systems and permits exchange of data among the ports and memory interface systems. A path allocation system controls the switch module and allocates the data paths therethrough. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the ports. The destination queues are implemented with a double link list in a single memory configuration so that a separate queue structure in hardware is not necessary. Moreover, the scheduler is implemented with a digital signal processor (DSP) with on-chip memory so that the queues are implemented within the on-chip memory and can be accessed at high speed.

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Toronto, Canada

Robin Purohit