United Microelectronics Corp.

United Semiconductor Corp.

Other

Robin Lee

Chih-Hung Lin

Gary Y Hong

Anchor Chen

Hwi-Huang Chen

A method of manufacturing a V-shaped flash memory. The V-shaped stack gate is formed by implanting ions into a substrate to form a buried source line using a mask, and then forming a V-shaped trench that exposes the buried source line in the substrate. A V-shaped word line stack gate is next formed over the trench and the substrate next to the trench. A common drain terminal is formed in the substrate on each side of the V-shaped stack gate. The drain terminal is electrically connected to a bit line by forming a contact plug.

Method of manufacturing V-shaped flash memory

An outer air spacer structure, applicable to multilevel interconnects technologies, and the method of making the same are disclosed. The outer air spacer is adjacent to a metal line to provide a lower dielectric constant in a metal interconnect structure. The outer air spacer is formed by initially forming a first spacer adjacent to the metal line, followed by forming a second spacer on the first spacer. The first spacer is then removed to form an air gap between the second spacer and the metal line. The air gap is closed to form the outer air spacer by partially sealing the air gap with a portion of passivation layer that is deposited subsequently.

Method of fabricating metal interconnect structure having outer air spacer

A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Fabrication method for a two-bit flash memory cell

A fabrication method for a dynamic random access memory is described, wherein after the formation of the shallow trench in the substrate to define the active region, an isolation structure is formed in the shallow trench. A first conductive layer is formed to cover the substrate and to fill the shallow trench. A portion of the first conductive layer is removed, leaving only the portion in the shallow trench to form a bit line in the shallow trench. Thereafter, an elevated portion is formed on the substrate, connecting the bit line to the active region where the source region is to be formed. A transistor is then formed in the active region. The area of the source region of the transistor includes the substrate under the elevated part, wherein the source region is connected to the second conductive layer. A dielectric layer is further formed covering the substrate, followed by forming a capacitor on the dielectric layer, wherein the capacitor passes through the dielectric layer to connect with the transistor.

Method for fabricating a buried bit line in a DRAM cell

A fabrication method for an air-gap, in which method hard mask is used, is described. A patterned hard mask layer is formed on a semiconductor substrate. Taking advantage of the etching selectivity of the hard mask layer to the dielectric layer, an opening with a high aspect ratio is formed in the dielectric layer. A conductive plug is then formed in the opening, followed by forming a conductive layer on the hard mask layer to cover the conductive plug. The hard mask layer is further removed. A silicon oxide layer with poor step coverage is formed to cover the substrate. Using the space remaining after the removal of the hard mask layer, an air-gap is formed between the conductive layer and the dielectric layer to enhance the insulation effect.

Method for fabricating an air-gap with a hard mask

A flash memory cell structure and its method of manufacture. The flash memory cell has a vertical configuration. An opening and then a trench are formed in a substrate by etching. The trench (defined as the recessed section of the substrate) is used for forming a shallow trench isolation structure. The substrate region between two neighboring openings (defined as the protruding section of the substrate) is used for forming a common drain and a channel. A source terminal is formed in the substrate at the upper comer next to the shallow trench structure. A tunnel oxide layer is formed over the substrate surface of the opening. A floating gate and a dielectric layer are formed over the tunnel oxide layer. A control gate is formed inside the opening.

Flash memory structure and method of manufacture

A fabrication method for an ultra short channel device comprising a self-aligned landing pad is described in which a first opening is formed in the oxide layer to define a gate structure region. A pad oxide layer is then formed in the first opening covering the substrate followed by forming a spacer on the inner sidewall of the first opening. Using the spacer as an etching mask, a portion of the oxide layer is removed to form a second opening exposing the substrate. A gate oxide layer is then deposited in the second opening, followed by forming a first conductive layer to fill the second opening. A third opening is then formed in the oxide layer to expose the substrate and to define the source/drain region. An ion implantation is then conducted in the substrate of the third opening to form a heavily doped region of the source/drain region. Thereafter, a landing pad is formed to fill the third opening and to electrically connect with the source/drain region. The spacer is then removed to form a fourth opening in the exposed pad oxide layer. An ion implantation is then conducted in the substrate of the fourth opening to form the lightly doped region.

Fabrication method for ultra short channel device comprising self-aligned landing pad

A method for fabricating a flash memory cell is described. A conformal ultra thin oxide layer is formed on a substrate having a trench formed therein, followed by forming silicon nitride spacers on the portion of the ultra thin oxide layer which covers the sidewalls of the trench. The silicon nitride spacers are separated into a first silicon nitride spacer on the right sidewall and a second silicon nitride spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the silicon nitride spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Trench flash memory with nitride spacers for electron trapping

A method for manufacturing dynamic random access (DRAM) memory. A substrate has a plurality of active regions marked out by shallow trench isolation (STI) structures therein. A conductive layer and a barrier layer are formed over the substrate. The conductive layer and the barrier layer are patterned to form bit line contact openings and node contact openings so that a portion of the active region and the shallow trenches are exposed. In the meantime, a word line inside the active region is also patterned out. Source/drain terminals are formed in the active regions. A bit line plug is formed inside each bit line contact opening, and a landing pad is formed inside each node contact opening. An oxide layer is formed over the bit line plugs and the landing pads. A word line patterning operation is conducted to establish the word line structures. A first dielectric layer is formed over the substrate, and then a bit line structure that connects with the bit line plug is formed in the first dielectric layer. A second dielectric layer is formed over the first dielectric layer, and finally a capacitor that connects electrically with a landing pad is formed above the second dielectric layer.

Method for manufacturing dynamic random access memory

A fabrication method for a metal interconnect having an inner air spacer, applicable to multilevel interconnects technologies, is disclosed. The inner air spacer is formed adjacent to a metal layer to provide a lower dielectric constant in a metal interconnect structure. The inner air spacer is formed by initially forming a dielectric spacer on a sidewall of a second dielectric layer, which sidewall defines a trench opening. The trench opening is then filled with the metal layer. The dielectric spacer is removed to form an air gap between the metal layer and the second dielectric layer. The air gap is sealed off with a portion of a third dielectric layer to form the inner air spacer adjacent to a sidewall of the metal layer.

Method of fabricating metal interconnect having inner air spacer

A method of manufacturing a two-bit flash memory. A substrate has a thin oxide layer, a silicon nitride layer and a material layer formed thereon in sequence. An opening is formed in the material layer and the silicon nitride layer to expose a portion of the thin oxide layer. A source/drain region is formed in the substrate beneath the portion of the thin oxide layer exposed by the opening. A first dielectric layer is formed in the opening. A portion of the material layer and a portion of the silicon nitride layer are removed to form a spacer on the sidewall of the first dielectric layer. The remaining material layer is removed. A portion of the thin oxide layer exposed by the remaining silicon nitride layer and the first dielectric layer is removed. A second dielectric layer is formed on a portion of the substrate exposed by the remaining thin oxide layer. A control gate is formed over the substrate.

Method for manufacturing two-bit flash memory

A method for fabricating a self-aligned ultra short channel. The method uses double spacers as a hard mask, so that DRAM with the ultra short channel is formed in a self-aligned process. This method not only reduces the channel length, but also adjusts the dopants in lightly doped drains (LDD) at a side of the storage node opening and at the side of the bit line, respectively, so as to optimize the device property.

Method of fabricating self-aligned ultra short channel

A method of fabricating an ETOX flash memory. A low-resistance source line is formed on the substrate to string each source region in one source array by self-aligned process to substitute conventional buried source line. And at the same time, landing pads are formed on the each drain region by a self-aligned process to reduce the fabrication difficulty of the contact plug.

Method of fabricating an ETOX flash memory

A dynamic random access memory structure. The structure includes a substrate having protruding sections and recessed sections, in which the protruding sections have sidewalls and a substrate surface is located between the protruding sections and the recessed sections. A gate oxide layer is formed on the sidewalls of the protruding sections and on the surfaces between the protruding sections and the recessed sections. A doped region is formed near the bottom of each protruding section, and these doped regions serve as buried bit lines. A channel region is formed in the protruding section and a gate electrode is formed on each side of the channel region. A storage electrode is connected to the other end of the protruding section and a word line is connected to the gate electrode. The word line and the buried bit line are perpendicular to each other.

Dynamic random access memory structure

A Method for forming a dynamic random access memory device with an ultra-short channel and an ultra-shallow junction is described in the invention. In the invention, the spacer is used as a mask to define the channel length of the device, so that the channel length of the device is not limited by the resolution of the photolithography process, and the performance of the device is improved thereby. Furthermore, an inversion layer serves as a junction to reduce the electric field; thus, the reliability of the device is increased.

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Hsinchu Hsien, Taiwan

Robin Lee