Winbond Electronics Corporation

Other

Nexcom Technology, Inc.

Integrated Silicon Solution Incorporated

Nexflash Technologies, Inc.

Ict International Cmos Technology, Inc.

Ict International Cmos Tech., Inc.

Robin John Jigour

Oron Michael

Hui W Chen

David K Wong

Eungjoon Park

Anil Gupta

Ali Pourkeramati

Shueh-Mien J Lee

Masaru Yano

Asim A Bajwa

Joo Weon Park

Jong Seuk Lee

Jooweon Park

Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR ('HPSF-NOR') memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND ('SPSF-NAND') memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low &#x201c;cost per bit&#x201d; and low per bit power consumption of a NAND memory array at higher densities.

NAND flash memory

NAND flash memory device

Method of operating a NAND flash memory device

Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented 'on chip' in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.

On-chip bad block management for NAND flash memory

A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Flash memory for code and data storage

A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.

Method and apparatus for reading NAND flash memory

A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Serial flash semiconductor memory

Each device of a family of removable digital media devices (,and,) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (,and,) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (,and,) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required. In particular, a small number of durable contact pads form the contact arrays (,and,) on the digital media devices, which in conjunction with corresponding contact pads mounted into a suitable socket provide for easy and convenient insertion and removal and for robust and reliable electrical contact over a long insertion lifetime. Preferably, the digital media devices of the family incorporate flash memory, which permits low voltage operation, low power consumption, and high capacity non-volatile data storage. Preferably, the digital media devices of the family are fabricated using surface mount techniques (,and,) or particularly inexpensive &ldquo;Chip on Board&rdquo; techniques (,and,). The digital media devices interface to the host either directly or through adapters. Access is handled either by a dedicated controller or other logic residing in the adapter or on the host, or by software running on the host.

Insertble and removable digital memory apparatus

Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required. In particular, a small number of durable contact pads form the contact arrays (314, 324, 334, 344, 354 and 364) on the digital media devices, which in conjunction with corresponding contact pads mounted into a suitable socket provide for easy and convenient insertion and removal and for robust and reliable electrical contact over a long insertion lifetime. Preferably, the digital media devices of the family incorporate flash memory, which permits low voltage operation, low power consumption, and high capacity non-volatile data storage. Preferably, the digital media devices of the family are fabricated using surface mount techniques (310 and 320) or particularly inexpensive 'Chip on Board' techniques (330, 340, 350 and 360). The digital media devices interface to the host either directly or through adapters. Access is handled either by a dedicated controller or other logic residing in the adapter or on the host, or by software running on the host.

Insertable and removable high capacity digital memory apparatus and

A memory device (100) includes a user device information sector (122) in addition to normal sectors (124) of a memory array. The user device information sector includes a product identification field (240) and a restricted address list field (250), and optionally includes a customer identification number field (220) and a serial number field (230). The product identification field includes such information as the manufacturer ID, a part number ID, package/speed identification, temperature/voltage identification, and byte locations for special options. The device identification field is factory programmed using a high voltage enabling signal applied to a write control logic circuit (102) in the memory device in conjunction with a 'Device Information Sector Program' instruction is applied to the SPI command and control logic (110). The device information sector is read from the application using a 'Read Device Information' instruction. Inadvertent corruption of the device information sector is avoided since a high voltage typically is not available in the application, and the 'Device Information Sector Program' instruction is not in the application command set.

Method and apparatus for providing accessible device information in

Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required. In particular, a small number of durable contact pads form the contact arrays (314, 324, 334, 344, 354 and 364) on the digital media devices, which in conjunction with corresponding contact pads mounted into a suitable socket provide for easy and convenient insertion and removal and for robust and reliable electrical contact over a long insertion lifetime. Preferably, the digital media devices of the family incorporate flash memory, which permits low voltage operation, low power consumption, and high capacity non-volatile data storage. Preferably, the digital media devices of the family are fabricated using surface mount techniques (310 and 320) or particularly inexpensive 'Chip on Board' techniques (330, 340, 350 and 360).

Insertable/removable digital memory apparatus and methods of operation

Adapter for interfacing an insertable/removable digital memory apparatus

A programmable logic device having greater design flexibility through use of a plurality of programmable macrocells in conjunction with programmable gate arrays. Each macrocell includes a programmable reconfigurable register for receiving sum terms from the array, and an I/O terminal connected to receive an output from the programmable reconfigurable register. Two separate feedbacks from the macrocell to the gate array are provided. The first feedback has multiple inputs including the register output, and the second feedback has multiple inputs including the I/O terminal. Accordingly, the I/O terminal and the register can function independently. Each sum term is capable of serving multiple functions as determined by the programming of the macrocell whereby the input terms can be utilized to implememt two completely independent sum-of-product logic functions, both combinatorial and one combinatorial and one sequential, and whereby each is capable of being programmably routed as feedback to the array or as an output to the I/O terminal.

High-performance user programmable logic device (PLD)

A programmable logic device having greater design flexibility through use of a plurality of programmable macrocells in conjunction with programmable gate arrays. Each macrocell includes a programmable reconfigurable register for receiving sum terms from the array, and an input/output (I/O) terminal connected to receive an output from the programmable reconfigurable register. Two separate feedbacks from the macrocell to the gate array are provided. The first feedback has multiple inputs including the register output, and the second feedback has multiple inputs including the I/O terminal. Accordingly, the I/O terminal and the register can function independently. Each sum term is capable of serving multiple functions as determined by the programming of the macrocell whereby the input terms can be utilized to implement two completely independent sum-of- product logic functions, both combinatorial and one combinatorial and one sequential, and whereby each is capable of being programmably routed as feedback to the array or as an output to the I/O terminal.

Growing community of inventors

San Jose, CA, United States of America

Robin John Jigour