Lsi Logic Corporation

Robin H Passow

Gordon W Priebe

Thomas R Wik

Kevin R LeClair

Myron J Buer

Ronald D Isliefson

Ken Redding

I Ross Mactaggart

A method is provided for using twisted bit or signal lines and routing restrictions on the logic signal lines to pass logic signals over an on-chip memory. In one embodiment, the memory array includes complementary bitlines which are provided with periodic twists, and the logic signal routing is restricted in that logic signals are either routed perpendicular to the bit lines, or they are routed parallel to the bit lines in such a manner as to ensure equal coupling to both B and B'. The equal coupling is provided by either restricting the length of the logic signal line segment to an integral number of twist wavelengths, or by placing the logic signal line segment so that its midpoint rests on a twist centerline. In another embodiment, the memory array includes bitlines running parallel to a bitline axis, and complementary logic signal lines are routed in pairs. The logic signal routing is restricted in that logic signals are either routed perpendicular to the bitline axis, or they are routed parallel to the bitlines in such a manner as to ensure equal coupling to both B and B'. The equal coupling is provided by either placing a twist at the midpoint of the complementary logic signal line segment, or by placing periodic twists in the complementary logic signal line segment and restricting the length of the segment to an integer number of twist wavelengths.

Method and system which permits logic signal routing over on-chip

A fast memory system including one or more asymmetrical sense amplifiers precharged to a first logic state and optimized to slew very fast towards the first logic state. Each sense amplifier is coupled to a corresponding pair of complementary bit lines, which are preferably precharged. When enabled, each sense amplifier tends towards an opposite, default logic state opposite the first logic state when sensing the precharged bit lines. Control logic enables a corresponding precharge amplifier to precharge the bit lines, and then enables the sense amplifier after the assertion of a clock signal. Also, the control logic enables a corresponding pull-up device to precharge the output of each sense amplifier. Thus, the sense amplifier begins in the first, precharged logic state and slews towards the opposite, default logic state. The control logic then asserts a word line select signal to a corresponding memory cell, which drives a voltage differential on the bit lines to assert a data bit. If the data bit supports the default state, then the sense amplifier switches to the default state. However, if the data bit supports the first state, the sense amplifier quickly responds and slews back to the first state. In this manner, either logic state is achieved very quickly. Preferably, an invertor is coupled to the sense amplifier having an input switch-point set to favor the default logic state.

Fast memory sense system

A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver receives the enable signal and asserts a select signal on a dummy select line, which causes a memory access to occur in the dummy portion simultaneously with each access of the core memory array. A fixed memory cell in the dummy path always asserts a logic zero to a dummy sense amplifier, which senses the logic zero and respondingly asserts a timing signal. The dummy sense amplifier is biased with a voltage offset to favor a logic one, so that the timing signal is preferably delayed until after the output data of the core memory array has stabilized. The control logic detects the assertion of the timing signal and respondingly latches the output data, and the control logic also shuts down the sense amplifiers to prevent further power drain. In this manner, the output data is latched and the sense amplifiers are disabled as soon as possible to conserve energy but within a safe timing margin to assure that valid data is properly latched. A biased inverter is preferably added for further timing margin. The sense amplifiers preferably include an input level-shifter stage for proper operation at low voltage levels.

Method and apparatus for a low power self-timed memory control system

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Maple Plain, MN, United States of America

Robin H Passow