International Business Machines Corporation

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Robin H Chao

Nicolas J Loubet

Choonghyun Lee

Jingyun Zhang

Chun Wing Yeung

James J Demarest

Shay Reboh

Remi Coquand

Rémi Coquand

Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.

Bottom channel isolation in nanosheet transistors

A method is provided of fabricating a microelectronic device including a semiconductor structure provided with semiconductor bars positioned above one another, the method including the following steps: creating, on a substrate, a stacked structure including an alternation of first bars containing a first material and having a first critical dimension and second bars containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions of the second bars before forming a source and drain block on the portions.

Method for forming doped extension regions in a structure having superimposed nanowires

Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.

Vertically integrated nanosheet fuse

Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having uniform low-k inner spacers. A nanosheet stack is formed opposite a major surface of a substrate. The nanosheet stack includes multiple nanosheets. Cavities are formed between adjacent ones of the multiple nanosheets. The cavities are filled with an oxide material and portions of the oxide material are nitridized to form inner spacers positioned between the adjacent ones of the multiple nanosheets.

Uniform low-k inner spacer module in gate-all-around (GAA) transistors

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Wappingers Falls, NY, United States of America

Robin H Chao