Texas Instruments Corporation

Robin Gupta

Abishek Manian

Yonghui Tang

Surya Theja Golakonda

A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

Receiver with pre-cursor intersymbol interference mitigation

Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.

Coarse equalizer adaptation and rate detection for high-speed retimers

A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.

Self-referenced clockless delay adaptation for random data

A loss of lock detection circuit includes detection circuitry and pulse accumulation circuitry. The detection circuitry includes a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is configured to synchronize a data stream to a first edge of a clock signal. The second flip-flop is configured to synchronize the data stream to a second edge of the clock signal. The third flip-flop is clocked by the data stream, and is configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream. The pulse accumulation circuitry is coupled to the detection circuitry. The pulse accumulation circuitry is configured to collect pulses generated by the third flip-flop.

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Santa Clara, CA, United States of America

Robin Gupta