W. L. Gore & Associates, Inc.

Supercomputer Systems Limited Partnership

Robin E Gorrell

Paul J Fischer

Mark F Sylvester

David B Noddin

Michael R Leaf

William George Petefish

Jimmy Leong

Boydd Piper

Kevin L Stumpe

Deepak N Swamy

A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Dimensionally stable core for use in high density chip packages and a method of fabricating same

In a method for forming redundant signal traces and corresponding electronic components, a photoresist pattern which defines a semi-additive signal image is coated on at least one first conductive layer of a composite base substrate. A barrier layer of etch-resistant metal is deposited on the first conductive layer. The photoresist is removed, thereby forming a first barrier signal trace having a first line width. Optionally, one or more vias may be formed in the substrate. A surface conductive layer is deposited on the first conductive layer, the barrier layer, and on a surface of the optional vias. A photoresist pattern is coated on the surface conductive layer which defines a subtractive signal image. Predetermined portions of the surface conductive layer and the first conductive layer are removed. The photoresist is removed forming a second signal trace in overlying relationship with the first barrier signal trace and having a second line width greater than the first line width.

Method of forming redundant signal traces and corresponding electronic

A method of forming a via in a laminated substrate by forming ablated material by laser drilling a via in a laminated substrate. The ablated material is deposited on a sidewall of the via. An ultrasonic treatment is applied to the drilled substrate thereby removing ablated material redeposited on sidewalls of the via.

Method for using ultrasonic treatment in combination with UV-lasers to

Dimensionally stable core for use in high density chip packages

A method is provided for forming at least one raised metallic contact on an electrical circuit for permanent bonding. Generally, this method includes the following steps: providing a composite base substrate which is defined by at least a first conductive layer, a dielectric material and a second conductive layer; removing a portion of the first conductive layer to expose the dielectric material; removing the exposed portion of the dielectric material to the second conductive layer, thereby forming a depression; depositing at least one layer of solder on at least side wall portions of the depression; depositing at least one layer of copper; removing the second conductive layer; and completely removing the dielectric material to said first conductive layer thereby forming a raised solder contact which extends perpendicularly away from the first conductive layer.

Method of forming raised metallic contacts on electrical circuits for

A method is provided for forming at least one raised metallic contact on an electrical circuit. Generally, this method includes the following steps: providing a composite base substrate which is defined by at least a first conductive layer, a dielectric material and a second conductive layer; removing a portion of the first conductive layer to expose the dielectric material; removing the exposed portion of the dielectric material to the second conductive layer, thereby forming a depression; depositing at least one layer of conductive material on at least side wall portions of the depression; removing the second conductive layer; and completely removing the dielectric material to said first conductive layer thereby forming a raised metallic contact which extends perpendicularly away from the first conductive layer.

Method of forming raised metallic contacts on electrical circuits

A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and the top metal layer to form an area array interconnection without bonding the surrounding dielectric substrate.

Growing community of inventors

Eau Claire, WI, United States of America

Robin E Gorrell