Infineon Technologies Ag

Robin Boch

Gerd Dirscherl

Bernd Meyer

Jan Otterstedt

Steffen Sonnekalb

Christian Peters

Stefan Erdmenger

Udo Kriebel

A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

Memory circuit and method of operating a memory circuit

Memory circuit including overlay memory cells and method of operating thereof

A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

Memory circuit including at least one marking cell and method of operating said memory circuit

A method for monitoring the correct operations of a data processing device including changing a subsystem from an authorized state to an unauthorized state, executing the partial operating sequence, and resetting any subsystem state from the unauthorized state to the authorized state.

Data processing device and method for monitoring correct operation of a data processing device

Growing community of inventors

Holzkirchen, Germany

Robin Boch