Zarlink Semiconductor Limited

X Integrated Circuits B.v.

Robertus Laurentius Van Der Valk

Johannes Hermanus Aloysius De Rijk

Willem L Repko

Petrus W Simons

Paulus Hendricus Lodewijk Maria Schram

Craig Barrack

Menno Spijker

Douglas Sitch

Philip Ching

Menno T Spijker

Steven Roos

Jason Robert Rosinski, Jr

Gerrit Dijkstra

Paul Hendricus Lodewijk Maria Schram

Johannes H De Rijk

Robertus J Dequesnoy

A method is disclosed for recovering timing information between master and slave nodes interconnected over a packet network having an underlying time grid with a distinct granularity. A series timing packets are exchanged between said master and slave nodes to measure the time offset of the time grid relative to clocks at the master and slave clocks. This offset is then used to either adjust the local clock at the slave node, or generate the clock using a digital controlled oscillator.

Method of recovering timing over a granular packet network

A frequency synthesizer includes a first clock running at a frequency f, a second clock running at a frequency f, wherein frequency fis higher than frequency f, the frequencies having a fixed ratio Q=f/f; and a counter driven by the first clock. A decoder for produces Qoutput values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these Qoutput values at the frequency of the second clock.

Flexible waveform generator with extended range capability

A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.

Digital phase locked loop

A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.

Asynchronous phase acquisition unit with dithering

A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.

Fractional digital PLL

A method of recovering timing information in a packet network is disclosed wherein a modulation scheme is used to transport additional information required for clock recovery between the sender and receiver across the network.

Method to improve the resolution of time measurements and alignment in packet networks by time modulation

Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.

Alignment of clocks over multiple packet networks

The present invention is a method to rapidly lock a type II phase locked loop (PLL) after a frequency jump without degrading the output signal much. The method to decrease the settling time and improve the quality of the output clock during the settling disclosed herein comprises of the following broad steps: Estimate new frequency offset with a separate circuit outside the PLL loop to measure the frequency of the input signal accurately. Ramp integrator to the new frequency offset. Do phase build out or phase pull-in. The remaining phase offset is build out when no edge to edge alignment is required. Otherwise, the remaining phase offset is pulled in while the integrator in the PLL's loop filter is disabled. Reduce the PLL bandwidth and/or lower damping to let the PLL settle. Switch the PLL to final bandwidth and damping required by the application.

Phase locked loop fast lock method

Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.

Method providing distribution means for reference clocks across packetized networks

Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points. These steps are continually repeated on new sets of data points created from newly received synchronization packets using the current delay estimate for the expected delay. And a clock domain at the destination is continually aligned with a clock domain at the source based on the current delay estimate for packets traversing the network between the source and destination.

Alignment of clock domains in packet networks

A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.

Flexible decimator

A resampler filter for use in an analog phase-locked loop has a charge pump and one or more switched capacitors switched by signals derived from a voltage controlled oscillator in the phase locked loop.

Analog PLL with switched capacitor resampling filter

A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.

High speed digital counters

The method is capable of rapidly bringing a phase-locked loop subject to overshoot into lock after a phase or frequency jump. The phase-locked loop has a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of the controlled oscillator. The method includes the steps of storing a value for the output frequency setting of the integrator prior to the phase or frequency jump, determining when a phase hit occurs after the phase or frequency jump, and restoring the output frequency setting of the integrator to the stored value on or soon after the phase hit to reduce overshoot. In this way the degradation of PLL performance is minimized.

Growing community of inventors

Dordrecht, Netherlands

Robertus Laurentius Van Der Valk